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4.2.1
Alphabetical Signals Reference
Table 11.
Signal Description (Sheet 1 of 7)
Name
A[35:3]#
A20M#
ADS#
ADSTB[1:0]#
AP[1:0]#
BCLK[1:0]
®
®
Intel
Celeron
Processor 1.66 GHz/1.83 GHz
DS
30
®
®
Intel
Celeron
Processor 1.66 GHz/1.83 GHz—Package Mechanical Specifications and Pin
Type
A[35:3]# (Address) define a 2
phase 1 of the address phase, these pins transmit the address of a transaction.
In sub-phase 2, these pins transmit transaction type information. These signals
Input/
must connect the appropriate pins of both agents on the Intel
Output
Processor 1.66 GHz/1.83 GHz FSB. A[35:3]# are source synchronous signals
and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are
used as straps which are sampled before RESET# is deasserted.
If A20M# (Address-20 Mask) is asserted, the processor masks physical address
bit 20 (A20#) before looking up a line in any internal cache and before driving a
read/write transaction on the bus. Asserting A20M# emulates the 8086
processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M#
Input
is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the
TRDY# assertion of the corresponding Input/Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
Input/
activation to begin parity checking, protocol checking, address decode, internal
Output
snoop, or deferred reply ID match operations associated with the new
transaction.
Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and
falling edges. Strobes are associated with signals as shown below.
Input/
Output
REQ[4:0]#, A[16:3]#
A[35:17]#
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,
A[31:3]#, and the transaction type on the REQ[4:0]# pins. A correct parity
signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. This allows parity to be high when all the
covered signals are high. AP[1:0]# should connect the appropriate pins of all
front side bus agents. The following table defines the coverage model of these
signals.
Input/
Output
Request Signals
A[35:24]#
A[23:3]#
REQ[4:0]#
The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB
agents must receive these signals to drive their outputs and latch their inputs.
Input
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing V
Description
36
-byte physical memory address space. In sub-
Signals
Associated Strobe
ADSTB[0]#
ADSTB[1]#
Subphase 1
AP0#
AP1#
AP1#
.
CROSS
Information
®
®
Celeron
Subphase 2
AP1#
AP0#
AP0#
January 2007
Order Number: 315876-002
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