Package Low Power States; Normal State - Intel Pga478 - P4-2ghz 512kb 400mhz Fsb Datasheet

2.1.1.3 C1/MWAIT Powerdown State
MWAIT is a low power state entered when the processor core executes the MWAIT
instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state
except that there is an additional event that can cause the processor core to return to
the C0 state: the Monitor event. Refer to the
Software Developer's Manuals
information.
2.1.2

Package Low Power States

The following sections describe all package level low power states for the Intel
®
Celeron
2.1.2.1

Normal State

This is the normal operating state for the processor. Intel
GHz/1.83 GHz enters the Normal state when its core is in the Normal, AutoHALT, or
MWAIT state.
2.1.2.2 Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20
bus clocks after the response phase of the processor-issued Stop Grant Acknowledge
special bus cycle. Once the STPCLK# pin has been asserted, the Intel
Processor 1.66 GHz/1.83 GHz, the processor core must be in the Stop Grant state
before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the system bus, these pins should not
be driven (allowing the level to return to V
termination resistors in this state. In addition, all other input pins on the system bus
should be driven to the inactive state.
BINIT# is not serviced while the processor is in Stop-Grant state. The event is latched
and can be serviced by software upon exit from the Stop Grant state.
RESET# causes the processor to immediately initialize itself, but the processor stays in
Stop-Grant state. A transition back to the Normal state occurs with the de-assertion of
the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state,
STPCLK# should only be deasserted one or more bus clocks after the deassertion of
SLP#.
A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop
on the system bus A transition to the Sleep state occurs with the assertion of the SLP#
signal.
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] is latched by the
processor, and only serviced when the processor returns to the Normal state. Only one
occurrence of each event is recognized upon return to the Normal state.
While in Stop-Grant state, the processor processes snoops on the system bus and it
latches interrupts delivered on the system bus.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is
asserted if there is any pending interrupt latched within the processor. Pending
interrupts that are blocked by the EFLAGS.IF bit being clear still causes assertion of
PBE#. Assertion of PBE# indicates to system logic that it should return the processor to
the Normal state.
® ®
Intel Celeron Processor 1.66 GHz/1.83 GHz
DS
12
®
Intel
in
Processor 1.66 GHz/1.83 GHz.
®
Celeron Processor 1.66 GHz/1.83 GHz—Low Power Features
Intel® 64 and IA-32 Architectures
Volume 3A/3B: System Programming Guide
) for minimum power drawn by the
CCP
for more
®
® ®
Celeron Processor 1.66
® ®
Celeron
January 2007
Order Number: 315876-002