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Table 11.
Signal Description (Sheet 7 of 7)
Name
STPCLK#
TCK
TDI
TDO
TEST1
TEST2
THERMDA
THERMDC
THERMTRIP#
TMS
TRDY#
TRST#
V
CC
V
CCA
V
CCP
V
CCSENSE
VID[5:0]
V
SSSENSE
®
®
Intel
Celeron
Processor 1.66 GHz/1.83 GHz
DS
36
®
®
Intel
Celeron
Processor 1.66 GHz/1.83 GHz—Package Mechanical Specifications and Pin
Type
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the FSB and APIC units. The processor continues to snoop bus
Input
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is
an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
Input
as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
Input
serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
Output
the serial output needed for JTAG specification support.
Input
TEST1 must have a stuffing option of separate pull down resistors to V
Input
TEST2 must have a 51W +/- 5% pull down resistor to V
Other
Thermal Diode Anode.
Other
Thermal Diode Cathode.
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature
Output
to ensure that there are no false trips. The processor stops all execution when
the junction temperature exceeds approximately 125 °C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
TMS (Test Mode Select) is a JTAG specification support signal used by debug
Input
tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
Input
receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of both FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
Input
driven low during power on Reset.
Input
Processor core power supply.
Input
V
provides isolated power for the internal processor core PLLs
CCA
Input
Processor I/O Power Supply.
V
CCSENSE
Output
(V
). It can be used to sense or measure power near the silicon with little
CC
noise.
VID[5:0] (Voltage ID) pins are used to support automatic selection of power
supply voltages (V
are CMOS signals driven by the Intel
The voltage supply for these pins must be valid before the VR can supply V
Output
the processor. Conversely, the VR output must be disabled until the voltage
supply for the VID pins becomes valid. The VID pins are needed to support the
processor voltage specification variations. Refer to
these pins. The VR must supply the voltage that is requested by the pins, or
disable itself.
V
is an isolated low impedance connection to processor core V
Output
SSSENSE
be used to sense or measure ground near the silicon with little noise.
Description
is an isolated low impedance connection to processor core power
). Unlike some previous generations of processors, these
CC
®
Celeron
Information
.
SS
.
SS
.
®
Processor 1.66 GHz/1.83 GHz.
CC
Table 4
for definitions of
. It can
SS
January 2007
Order Number: 315876-002
to
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