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Package Mechanical Specifications and Pin Information—Intel
1.83 GHz
Table 11.
Signal Description (Sheet 6 of 7)
Name
PROCHOT#
PWRGOOD
REQ[4:0]#
RESET#
RS[2:0]#
RSP#
RSVD
SKTOCC#
SLP#
SMI#
January 2007
Order Number: 315876-002
Type
PROCHOT# (Processor Hot) goes active when the processor temperature
monitoring sensor detects that the processor has reached its maximum safe
operating temperature. This indicates that the processor Thermal Control Circuit
Output
(TCC) has been activated.
This signal may require voltage translation on the motherboard.
PWRGOOD (Power Good) is a processor input. The processor requires this signal
to be a clean indication that the clocks and power supplies are stable and within
their specifications. 'Clean' implies that the signal remains low (capable of
sinking leakage current), without glitches, from the time that the power supplies
are turned on until they come within specification. The signal must then
transition monotonically to a high state. PWRGOOD can be driven inactive at any
Input
time, but clocks and power must again be stable before a subsequent rising
edge of PWRGOOD. It must also meet the minimum pulse width specification
and be followed by a 2 ms (minimum) RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB
Input/
agents. They are asserted by the current bus owner to define the currently
Output
active transaction type. These signals are source synchronous to ADSTB[0]#.
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least two milliseconds after V
and BCLK have reached their proper specifications. On observing active RESET#,
Input
both FSB agents deasserts their outputs within two clocks. All processor straps
must be valid within the specified setup time before RESET# is deasserted.
There is a 55 ohm (nominal) on die pull-up resistor on this signal.
RS[2:0]# (Response Status) are driven by the response agent (the agent
Input
responsible for completion of the current transaction), and must connect the
appropriate pins of all FSB agents.
RSP# (Response Parity) is driven by the response agent (the agent responsible
for completion of the current transaction) during assertion of RS[2:0]#, the
signals for which RSP# provides parity protection. It must connect to the
appropriate pins of all processor front side bus agents.
Input
A correct parity signal is high if an even number of covered signals are low and
low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is
also high, since this indicates it is not being driven by any agent guaranteeing
correct parity.
Reserved/
These pins are RESERVED and must be left unconnected on the board. However,
No
it is recommended that routing channels to these pins on the board be kept
Connect
open for possible future use.
SKTOCC# (Socket occupied) is pulled to ground by the processor to indicate that
Output
the processor is present.
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state does not recognize snoops or interrupts. The processor
Input
recognizes only assertion of the RESET# signal, deassertion of SLP#, and
removal of the BCLK input while in Sleep state. If SLP# is deasserted, the
processor exits Sleep state and returns to Stop-Grant state, restarting its
internal clock signals to the bus and processor core units.
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
Input
handler.
If SMI# is asserted during the deassertion of RESET# the processor tristates its
outputs.
®
®
Celeron
Processor 1.66 GHz/
Description
®
Intel
Celeron
CC
®
Processor 1.66 GHz/1.83 GHz
DS
35
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