Electrical Specifications; Front Side Bus And Gtlref; Power And Ground Pins; Decoupling Guidelines - Intel Pga478 - P4-2ghz 512kb 400mhz Fsb Datasheet

Electrical Specifications—Intel
3.0

Electrical Specifications

3.1

Front Side Bus and GTLREF

Most Intel
Transceiver Logic (AGTL+) signalling technology. This signalling technology provides
improved noise margins and reduced ringing through low-voltage swings and controlled
edge rates. The termination voltage level for the Intel
1.83 GHz AGTL+ signals is V
data and address bus, signal integrity and platform design methods have become more
critical than with previous processor families.
The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
system board. Termination resistors are provided on the processor silicon and are
terminated to its I/O voltage (V
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog
signal simulation of the FSB, including trace lengths, is highly recommended when
designing a system.
3.2

Power and Ground Pins

For clean, on-chip power distribution, the Intel
GHz has a large number of V
connected to V
planes. Use of multiple power and ground planes is recommended to reduce IR drop.
The processor V
(Voltage ID) pins.
3.3

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate. Care must be taken in the board design to ensure that the
voltage provided to the processor remains within the specifications listed in
Failure to do so can result in timing violations or reduced lifetime of the component.
3.3.1 V Decoupling
CC
Regulator solutions need to provide bulk capacitance with a low effective series
resistance (ESR) and keep a low interconnect resistance from the regulator to the
socket. Bulk decoupling for the large current swings when the part is powering on, or
entering/exiting low-power states, must be provided by the voltage regulator solution.
For more details on decoupling recommendations, please refer to the
Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded
Implementations Supporting
January 2007
Order Number: 315876-002
® ®
Celeron Processor 1.66 GHz/1.83 GHz
® ®
Celeron Processor 1.66 GHz/1.83 GHz FSB signals use Advanced Gunning
= 1.05 V (nominal). Due to speed improvements to
CCP
CCP
(power) and V
CC
power planes while all V
CC
pins must be supplied with the voltage determined by the VID
CC
PGA478.
®
Celeron
).
® ®
Celeron
(ground) inputs. All power pins must be
SS
pins must be connected to system ground
SS
®
Intel Celeron
®
Processor 1.66 GHz/
Processor 1.66 GHz/1.83
Table
Embedded
®
Processor 1.66 GHz/1.83 GHz
7.
DS
15