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Package Mechanical Specifications and Pin Information—Intel
1.83 GHz
Table 11.
Signal Description (Sheet 4 of 7)
Name
DSTBN[3:0]#
DSTBP[3:0]#
FERR#/PBE#
FORCEPR#
GTLREF
HIT#
HITM#
IERR#
January 2007
Order Number: 315876-002
Type
Data strobe used to latch in D[63:0]#.
Signals
D[15:0]#, DINV[0]#
Input/
D[31:16]#, DINV[1]#
Output
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
Data strobe used to latch in D[63:0]#.
Signals
D[15:0]#, DINV[0]#
Input/
D[31:16]#, DINV[1]#
Output
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
FERR# (Floating-point Error) PBE# (Pending Break Event) is a multiplexed signal
and its meaning is qualified with STPCLK#. When STPCLK# is not asserted,
FERR#/PBE# indicates a floating point error when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using MS-
DOS*-type floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending break
event waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. When FERR#/PBE# is
Output
asserted, indicating a break event, it remains asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is active also causes an FERR#
break event.
For additional information on the pending break event functionality, including
identification of support of the feature and enable/disable information, refer to
the
Intel® 64 and IA-32 Architectures Software Developer's Manuals
3A/3B: System Programming Guide
CPUID Instruction application note (AP-485)
The FORCEPR# input can be used by the platform to force the Intel
Input
Processor 1.66 GHz/1.83 GHz system bus to activate the Thermal Control Circuit
(TCC). The TCC remains active until the system deasserts FORCEPR#.
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
Input
should be set at 2/3* V
if a signal is a logical 0 or logical 1.
Input/
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
Output
results. Either FSB agent may assert both HIT# and HITM# together to indicate
that it requires a snoop stall, which can be continued by reasserting HIT# and
Input/
HITM# together.
Output
IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction
Output
on the FSB. This transaction may optionally be converted to an external error
signal (e.g., NMI) by system core logic. The processor keeps IERR# asserted
until the assertion of RESET#, BINIT#, or INIT#.
®
®
Celeron
Processor 1.66 GHz/
Description
Associated Strobe
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
DSTBN[3]#
Associated Strobe
DSTBP[0]#
DSTBP[1]#
DSTBP[2]#
DSTBP[3]#
and the
Intel® Processor Identification and
application note.
. GTLREF is used by the AGTL+ receivers to determine
CCP
®
Intel
Celeron
in
Volume
®
®
Celeron
®
Processor 1.66 GHz/1.83 GHz
DS
33
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