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Mitsubishi Electric MELSEC iQ-R C Series Programming Manual page 44

Controller module
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Accessing other stations
The accessible devices of the CC-Link module on the other station are shown in the following table.
No.
Access target CPU
(1)
Basic model QCPU, high performance model QCPU, process CPU, redundant CPU, universal model QCPU
(2)
Q12DCCPU-V, Q24DHCCPU-V, Q24DHCCPU-LS, Q24DHCCPU-VG, and Q26DHCCPU-LS
(3)
Personal computer and intelligent device station
(4)
L02CPU, L26CPU-BT, L02CPU-P, L26CPU-PBT, L02SCPU, L26CPU, and L06CPU
(5)
RCPU
(6)
R12CCPU-V
: Accessible, : Not accessible
Device
Input relay
Output relay
Latch relay
Internal relay
Special relay
Annunciator
Timer (Contact)
Long timer (Contact)
Timer (Coil)
Long timer (Coil)
Counter (Contact)
Long counter (Contact)
Counter (Coil)
Long counter (Coil)
Timer (Current value)
Long timer (Current value)
Counter (Current value)
Long counter (Current value)
Data register
Special register
Index register
Long index register
File register
Refresh data register
Link relay
Link register
Link special relay
Retentive timer (Contact)
Long retentive timer (Contact)
Retentive timer (Coil)
Long retentive timer (Coil)
Link special register
Edge relay
Own station random access buffer
Retentive timer (Current value)
Long retentive timer (Current value)
Remote register for sending
Remote register for receiving
Own station buffer memory
SEND function (with arrival confirmation)
1 COMMON ITEMS
42
1.3 MELSEC Data Link Functions
Access method
X
Batch/random
Y
Batch/random
L
Batch/random
M
Batch/random
SM
Batch/random
F
Batch/random
T
Batch/random
LT
Batch/random
T
Batch/random
LT
Batch/random
C
Batch/random
LC
Batch/random
C
Batch/random
LC
Batch/random
T
Batch/random
LT
Batch/random
C
Batch/random
LC
Batch/random
D
Batch/random
SD
Batch/random
Z
Batch/random
LZ
Batch/random
R
Batch/random
ZR
Batch/random
RD
Batch/random
B
Batch/random
W
Batch/random
SB
Batch/random
ST
Batch/random
LST
Batch/random
ST
Batch/random
LST
Batch/random
SW
Batch/random
V
Batch/random
Batch/random
ST
Batch/random
LST
Batch/random
RWw
Batch/random
RWr
Batch/random
Batch/random
Batch/random
Access target CPU
(1)
(2)
(3)
(4)
*1
*1
*1
*1
*1
*1
*2
*2
*3
*3
(5)
(6)

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