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A negative level a t pin 8 turns U2 and U4 off which turns off Q1. Q1 determines when the search
ramp signal is routed to DC Compensation Amplifier A7. The search ramp signal is derived from
the search pulse signal which is supplied from Search Programmer A6. U1 and U3 function as a n
integrator to provide a ramp voltage output. C7 is the integrating capacitor and R15 sets the dc
level for the ramp signal.
4-156. A6 SEARCH PROGRAMMER ASSEMBLY, 05340-60004
4-157. The Search Programmer (Figure 8-12) determines the search ramp amplitude and sets
the loop gain compensation. The circuits consist of counter U4, binary to decimal decoder U2,
buffer U1, loop compensation switches Q1 through Q6, search programming switches Q7
through Q12, and pulse conditioner U5.
4-158. Pulse conditioner U5 is a one-shot multivibrator used to shape the incoming start search
pulse from A21. C1 and R3 set the multivibrator pulse width at 5 milliseconds. The prf is deter-
mined by Control Assembly A21. The conditioned pulse is used by the Search Assembly A5 to
derive the search ramp signal.
4-159.
The counter circuit U4 receives three-line binary data and a strobe from interface
assembly A19. In addition, U4 receives the inhibit control and start search signals from A21.
These are used to drive the clock 2 input and the reset input of U4. The strobe input allows
parallel-entry for the DB, DC, and DD inputs. When the strobe line receives a logic 0, the data
inputs are transferred to the D,
negative going edge of the input clock pulse. The count function will start from the number
a binary-to-decimal decoder U2. U2 provides
of operation, assume that U2 receives A=H, B=H, and C=L. With this input, the 3 line (pin 4) goes
low to drive Ul(4) high. With Ul(4) high, Q4 and QlO are on and all other FET's are off. For
this programming segment, R11, C8, and R19 provide the proper loop compensation and R25
sets the search amplitude. Two modes of operation can be selected, normal and programmed.
4-160. A7 D C AMPLIFIER/COMPENSATOR NO. 1 ASSEMBLY, 05340-60005
4-161. A7 (Figure 8-13) consists of lock mode switches Ql, Q2, Q3, Q6, and dc amplifiers
Q4, Q5, QS, Q9. The lock mode switches are controlled by the search switch signal from A5 and
the input loop lock from A5. The output from Phase Detector No. 1 represents the error signal
required to drive VCO No. 1 to be phase coherent with the 20 MHz reference signal. When Q2 is
on, the phase detector signal is amplified by U1. R13 sets the dc level output. R27 sets the gain
of Q4
and
QS.
Diodes CR5 and CR8 provide limits
4-162. A8 BANDPASS FILTEWPHASE DETECTOR ASSEMBLY, 05340-60006
4-163. The BPF/Phase Detector Assembly (Figure 8-14) consists of a bandpass filter amplifier
and high impedance amplifiers Q1A and Q1B. A8 receives the 20 kHz reference signal from
Time Base A20 and the 20 kHz mixer signal from Mixer A l l . A8 produces two outputs: the trans-
fer loop SEARCH signal and the phase detector 2 signal. The transfer loop SEARCH signal is
sent to DC Compensator Amplifier A9. A9 uses the transfer loop SEARCH signal as a n indi-
cation of loop lock. The phase detector 2 output is used to drive VCO 2 s o that the 20 kHz mixer
signal is coherent with the 20
4-164.
The input to'Ul',is the mixer output from A l l at approximately 1V peak-to-peak
amplitude. U1 is a n operational amplifier connected in a bandpass filter feedback configuration.
The filter is tuned to 20 k g z with a Q of about 2 and a bandpass of *5 kHz at the 3 dB points.
,
4-165. Comparator u 2 compares the output level of U1 with the positive level set by R13. When
the output level of U1 exceeds the level set by R13, U2 produces
U3B is a retriggerable one-shot multivibrator. When U3B pin 12 goes high, the multivibrator
triggers to drive U3B pin 10 high for approximately 50 psec. The duration of the 50 psec
C,
and B outputs (U4 pins 12, 2, and 9). Counting occurs on the
a decimal output between 0 and 6. As a n example
the
for
maximum dc.
Model 5340A
Theory of Operation
a
positive output to trigger U3B.
and
4-39
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