Simplified Block Diagram Description; Overall Theory Of Operation; Input Circuits - HP 5340A Operating And Service Manual

Model 5340A
Theory of Operation

4-103. SIMPLIFIED BLOCK DIAGRAM DESCRIPTION

4-104. Figure 4-45 illustrates the simplified block diagram for the 5340A Frequency Counter.
The counter h a s five major functional circuit groups; the input-phase lock loop, the transfer
phase lock loop, the
4-105. Two separate inputs are provided for frequency measurements: the high impedance-low
frequency (10 Hz
direct c o m t path with high input impedance. The 10 Hz to 18 GHz input path either counts
directly from
18
quency to a countable range.
F,
4-106.
first disp bles the transfer oscillator circuits while the counter "looks" for a direct count input
from 10 Hz to -225 MHz. If there is a n input signal between 10 Hz and -225 MHz, the counter
establishes a direct count path. Signal flow is through the power divider and sampler (inactive)
to the counter circuits. Whkn a direct count path is established, the phase lock loops are kept
inactive. If a direct count is not established within approximately 10 milliseconds, the transfer
oscillator circuits are activated and the input phase lock loop searches for the presence of signals
between -225 MHz and 18 GHz. If two or more signals are encountered, the phase lock loop
acquires the signal with the larger amplitude.
I
which is harmonically related to the value of F , as follows:
integer equal to the harmonic relationship between
4-108. When the input phase lock loop locks, the transfer phase lock loop locks to provide a fre-
quency output from the
-
4-109. The interface board for the standard instrument provides the control signals required
for completing and displaying a measurement. The interface board for Option 011 provides for
digital output data and remote programming in addition to supplying control signals.

4-110. OVERALL THEORY OF OPERATION

The overall block diagram for the 5340A is located in Section VIII on a foldout sheet.
4-111.
See Figure 8-6.

4-112. Input Circuits

4-113. Two separate input pabhs are used: a high impedance direct count path
via input amplifier A3, and d l 0 Hz to 18 GHz path through power divider CP1, A1 and A2. When the
input frequency to C P l is'between 10 Hz and 250 MHz, a direct count path is used consisting of
4-32
N determination circuits, the counter circuits, and the interface circuits.
250 MHz) input, and the 10 Hz to 18 GHz input. The high
-
Hz to -225 MHz or uses a transfer oscillator technique to count from -225 MHz to
represents frequencies to be counted from 10 Hz to 18 GHz. The counter program
N
determination circuits which is proportional to N. Since F,
the counter h a s the necessary information to calculate and display the value of
Z
-
F,
20
and F1.
(10 Hz to 250 MHz)
input provides a
N is a n
=
F,.
i