J-K Flip-Flop 1820-0065; Decade Counter 1820-0055 - HP 5340A Operating And Service Manual

INPUT
NC
A ZA ZD GND
INPUT
DECADE COUNTER

4-15. J-K Flip-Flop 1820-0065

4-16. Figure 4-5 shows the logic diagram, outline drawing, and truth table for the 1820-0065
J-K flip-flop. The flip-flop is a n edge-triggered type having direct clear and preset inputs. Input
information will tzansfer to the outputs on t_he positive edge of the clock pulse. The J input is
defined as 51.52.5. The K input is Kl.K2*K, i.e., when J1 and 52 are high and
J
When and K are both low, the clock pulses have no effect. Whsn
positive clock transition will set the flip-flop so that Q is high and Q is low. When K i s high and
is low, the positive clock transition will reset the flip-flop so that Q is low and Q is high. If
both J and K are high, the flip-flop will change states (toggle) with each positive clock transition.
A low input at pin 13 will set the flip-flop and a low input to pin 2 will reset the flip-flop. The
clock must be a t logic 0 before set or reset pulses are applied.
PRESET
,
,
LOW I N P U T
Figure 4-4. Decade Counter 1820-0055
BCD COUNT SEQUENCE
(SEE NOTE
Figure 4-5. J-K Flip-Flop 1820-0065
CLK
T R U T H
NOTE
CLOCK MUST B E AT LOGICAL
PRIOR TO T H E APPLICATION OF
PRESET
NOTES
J - K F L I P - F L O P
I J=JI. J 2 .
POSITIVE LOGIC
o
PRESET S E T S TO LOGICAL I
T O C L E A R SET
4
Theory of Operation
TRUTH TABLES
RESET /COUNT
(SEE NOTE 2 )
2. X INDICATES THAT EITHER
A LOGICAL OR A LOGICAL
I
0 MAY BE PRESENT
J is high and K is low, the
T A B L E
0
OR CLEAR FUNCTIONS
BEFORE CLOCK PULSE
BIT TIME AFTER CLOCK PULSE
Model 5340A
J
is low, 1.
J
i
4-5