Low-Power 4-Bit Shift Register 1820-0659 - HP 5340A Operating And Service Manual

4-59. Low-Power 4-Bit Shift Register 1820-0659

4-60. Figure 4-27 shows the logic diagram and pin connections for the 1820-0659.
is provided for the first flip-flop in the register. This arrangement requires
input. A D-type input can be obtained by tying the
for all four stages are provided.
synchronous with the clock input, whenever the parallel enable input is low. When the parallel
enable input is low, the unit appears as four clocked D fli?-flops. When the parallel enable is
high, the shift register performs a one-bit shift for each clock input. Clocking occurs after the
low to high transistion of the clock input. Activie high outputs are provided for all four stages
and a n active low output is also provided for the last stage
stages to be set to zero independent of all input conditions.
Figure 4-27. Low-Power 4-Bit Shift Register 1820-0659
=
8
G N D = Pin
-
T A B L E I S E R I A L E N T R Y
=
=
L
H
at (toggles)
H H H
-
T A B L E S E R I A L E N T R Y
HIGH , HIGH)
=
=
Connected
,
J
a n d
These determine the next conditions of the shift register
P I N N A M E S
Clock (Active H I G H Going Edge) I n p u t
Master Reset (Active LOW1 I n p u t
Parallel Outputs
Complementary Last Stage Output
o r P g l
I
L
I
H
-
T A B L E I V M O D E S E L E C T I O N
Serial Entry
H H I G H Voltage Level
L LOW Voltage Level
X D o n ' t Care
Model 5340A
Theory of Operation
A
a
low to activate the
inputs together. Parallel inputs
The master reset input allows all
Parallel Inputs
First Stage J (Active H I G H ) I n p u t
First Stage K (Active L O W ) I n p u t
O u t p u t 0 at t n t 1
I
L
I
I
H
Table I &
input
4-19