Eight-Bit Serial-In Parallel-Out Shift Register 1820-0294; Bcd To Decimal Decoder 1820-0426; Voltage Comparator/Buffer 1820-0475; Theory O F Operation (Continued) - HP 5340A Operating And Service Manual

Model 5340A
Theory of Operation

4-31. Eight-Bit Serial-In Parallel-Out Shift Register 1820-0294

4-32. This IC (Figure 4-13) accepts serial input data and provides parallel outputs. The unit con-
sists of eight RS flip-flops connected in a shift register configuration. Clocking occurs on the
positive going edge of the clock pulse. Input gates are provided for the RS inputs to allow for
strobe capability. Logic 1 levels at SA and SB enter logical "1's" into the shift register. When the
clear input (pin 9) is driven low, all flip-flops are asynchronously set to the logical 0 state.
Figure 4-13. Eight-Bit Serial-In Parallel-Out Shift Register 1820-0294
L

4-33. BCD to Decimal Decoder 1820-0426

4-34. The decoder (Figure 4-14) is a BCD to one-of-ten decoder capable of driving gas-filled
cold-cathode indicator tubes. As a n example of operation, if the input is D=O C=O
then the 3 output at pin 9 will go low to turn on the numeral 3 in a n indicator tube.

4-35. Voltage Comparator/Buffer 1820-0475

4-36. This IC is shown in Figure 4-15 and serves as a high-speed voltage comparator to detect
low level analog signals and drive digital loads. The unit can drive RTL, DTL, or ?TL circuits.
4-10
A
I
9
14 13 12 11 10
1 2 3 4 5 6
I
I
7
B=l and A = l ,
=