Table of Contents
Advertisement
Model 5340A
Theory of Operation
4-45. Dual Two-Input Logic Switch 1820-0560
4-46. The logic switch (Figure 4-20) functions as a single pole, double throw switch for EECL
logic signals. The C input controls selection of either the A or B input; similarly, the F input
controls the D and E input selection. Complementary 50 ohm outputs are provided from the out-
put gates.
Figure 4-20. Dual Two-Input Logic Switch 1820-0560
POSITIVE LOGIC "1"
D
5
,
E
GND
I
16
4-47. Dual D-Type Edge-Triggered Flip-Flops 1820-0596
This IC contains low-power dual edge-triggered flip-flops
4-48.
mation at the D-input is transferred to the Q output on the positive-going edge of the clock pulse.
Clock triggering occurs a t a voltage level of the clock pulse and is not directly related to the
transition time of the positive-going pulse. When the clock is at either a high or low level, the D-
input signal h a s no effect. Maximum clock frequency is typically 3 MHz with a typical power
dissapation of 4.25 milliwatts per flip-flop.
4-49. Four-Input Multiplexer 1820-0610
4-50. The 1820-0610 (Figure 4-22) consists of two 4-line input multiplexers with common input
select logic. This configuration allows two bits of data to be switched in parallel to the approp-
riate outputs from two 4-bit data sources. Complementary outputs are provided. The truth table
for the multiplexer is show9 belpw.
4-14
=
High
.
,
3
14
I
5
12
I
11
)
NOTE:
Virtual Gate, N o Delay
=
NEGATIVE LOGIC "1"
Low
=
=
High
I
I
16
11
in Figure
as shown
4-21.
3
14
6
13
Infor-
Advertisement
Table of Contents
Troubleshooting
