National Instruments PCI-6251 User Manual page 254

Time
*
t PFI
3
RTSI
PXI_STAR
t PFI_i, RTSI_i, PXI_STAR_i,
4
or other internal signal
t P0
7
t DI Sample Clock
8
†
t PFI (output) high
9
*
The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the
trigger group for a given condition (maximum or minimum timing). This difference can be useful when
two external signals will be used together and the relative timing between the signals is important.
†
When DI Sample Clock is routed to a PFI output pin, the pulse width of the output is independent of
the pulse width of the input. The pulse width is specified in a number of periods of the 80 MHz Timebase
Time Requirement
t PFI, RTSI, or
1
PXI_STAR
minimum period
t PFI, RTSI, or
2
PXI_STAR
minimum pulse
width
t Setup time from P0_i
5
to DI Sample Clock
t Hold time from DI
6
Sample Clock to
P0_i
Table B-22. DI Timing Delays
From
Table B-23. DI Timing Requirements
Condition
When used as DI
Sample Clock
When used as DI
Sample Clock
—
—
To Min (ns)
PFI_i 5.2
RTSI_i 2.0
PXI_STAR_i
DI Sample
Clock
P0_i
PFI (output)
PFI (output) One period of
low 80 MHz
Timebase
Min (ns)
NI 622x devices:
1000.0
NI 625x/628x
devices: 100.0
M Series User Manual
Max (ns)
6.2 18.2
2.5 5.0
1.5 3.5
3.5 9
4.7 20.1
8.0 29.8
Two periods
of 80 MHz
Timebase
Max (ns)
12.0
1.5
0
© National Instruments | B-29
22.0
6.0
—
—
—
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