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Time
t
Delay from _i to Convert Clock
9
Timebase
t
Delay from Convert Clock Timebase to
10
p_AI_Convert
t
Delay from Convert Clock Timebase to
11
Convert Clock, when exported to an
external terminal (POUT)
Figure B-8. Convert Clock and Any Internal Signal Timing Diagram
Table B-4. Convert Clock and Any Internal Signal Timing
Time
t
_i to p_AI_Convert in
12
external convert mode
Start Trigger
The Start Trigger is the signal that starts an AI acquisition. This signal can come from an external
source (through an external terminal) or from an internal source. One possible internal source is
a software-generated pulse. A multiplexer selects from all the possible sources (all of them at _i
level) and outputs a signal called Selected Start Trigger. Selected Start Trigger then gets sent to
the two timing levels in the AI section (the Convert Clock Timebase and the Sample Clock
Timebase timing level) for synchronization to each clock. Once the Convert Clock Timebase
timing domain has received a valid Start Trigger, the AI timing engine is ready to begin
generating converts, as soon as it receives a Sample Clock (beginning of a sample). Once the
Sample Clock Timebase domain has received a valid Start Trigger, the AI timing engine is ready
to begin generating Sample Clocks.
Table B-3. Convert Clock Timing (Continued)
Description
_i
p_AI_Convert
Description
Line
PFI
RTSI
STAR
—
PFI
RTSI
t
12
Line
Min (ns)
PFI
RTSI
STAR
M Series User Manual
Min (ns)
Max (ns)
16.2
39.1
16.0
38.8
15.5
36.1
6.0
13.0
4.6
10.8
4.6
10.5
Max (ns)
22.2
52.1
22.1
51.8
21.5
49.1
© National Instruments | B-9
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