National Instruments PCI-6251 User Manual page 253

Appendix B Timing Diagrams
Digital I/O Timing Diagrams
This section describes the timing delays and requirements of digital waveform acquisitions and
digital waveform generations.
Digital Waveform Acquisition Timing
To describe digital waveform acquisition timing delays and requirements, refer to the circuitry
shown in Figure B-37. In the figure, P0, PFI, RTSI, and PXI_STAR represent signals at
connector pins of the M Series device. The other named signals represent internal signals.
Figure B-37. Digital Waveform Acquisition Timing Circuitry
PFI, RTSI,
or PXI_STAR
Figure B-38 and Tables B-22 and B-23 describe the digital waveform acquisition timing delays
and requirements. Your inputs must meet the requirements to ensure proper behavior.
Figure B-38. Digital Waveform Acquisition Timing Delays
PFI, RTSI,
or PXI_STAR
PFI_i, RTSI_i,
or PXI_STAR_i
DI Sample Clock
PFI (Output)
B-28 | ni.com
PFI_i, RTSI_i,
or PXI_STAR_i
Other Internal
Signals
t
3
t
5
P0
t
7
P0_i
DO Waveform
DO Sample
Generation FIFO
Clock
t
1
t t
2 2
t
3
t t
4 4
t
6
t
7
t t
8 9
P0
PFI (Output)