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Time
t
Minimum Pulse Width
2
t
Minimum Period
3
t
Delay to Sample Clock
4
Timebase
t
Delay to Sync Sample Clock
5
Timebase
t
Delay to Convert Clock
6
Timebase
t
Delay to Sync Convert
7
Clock Timebase
Convert Clock
Convert Clock is the signal that determines when an analog to digital conversion is started. The
signal going to the ADC is called p_AI_Convert. Convert Clock also can be routed to several
external I/O terminals for external use. Convert Clock is always generated from the Convert
Clock Timebase signal, either directly or indirectly (by dividing it down using the SI2 counter).
If the SI2 counter is used, it is assumed that a reliable free-running clock is being used. Refer to
AI Timing Clocks
the
Sync Convert Clock Timebase. If the SI2 counter is not being used (external convert case), the
Convert Clock Timebase is assumed to be not free-running and the relationship between the
Convert Clock Timebase and the Sync Convert Clock Timebase is an asynchronous delay.
Whether the SI2 counter is used or not, the timing parameters in the generation of Convert Clock
are the same starting at the Convert Clock Timebase signal.
Table B-2. AI Timing Clocks Timing
Description
section for the timing relationship between Convert Clock Timebase and
Line
Min (ns)
—
—
PFI
RTSI
STAR
PFI
RTSI
STAR
PFI
RTSI
STAR
PFI
RTSI
STAR
M Series User Manual
Max (ns)
12.5
—
50.0
—
3.8
9.3
3.5
9.0
3.0
6.4
3.4
8.5
3.2
8.3
2.7
5.6
4.1
10.2
3.9
9.9
3.4
7.3
3.6
8.9
3.3
8.6
2.9
6.0
© National Instruments | B-7
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