National Instruments PCI E Series Programmer's Manual
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National Instruments PCI E Series Programmer's Manual

Register-level programmer manual, multifunction i/o boards for pci bus computers, register-level
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See also: User Manual
DAQ
PCI E Series Register-Level
Programmer Manual
Multifunction I/O Boards for PCI Bus Computers
PCI E Series RLPM
November 1998 Edition
Part Number 341079B-01

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Summary of Contents for National Instruments PCI E Series

  • Page 1 PCI E Series Register-Level Programmer Manual Multifunction I/O Boards for PCI Bus Computers PCI E Series RLPM November 1998 Edition Part Number 341079B-01...
  • Page 2 Singapore 2265886, Spain 91 640 0085, Sweden 08 730 49 70, Switzerland 056 200 51 51, Taiwan 02 377 1200, United Kingdom 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, Texas 78730-5039 USA Tel: 512 794 0100 © Copyright 1998 National Instruments Corporation. All rights reserved.
  • Page 3 Warranty The PCI E Series boards are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period.

  • Page 4: Table Of Contents

    Digital I/O Circuitry ..................2-24 Timing I/O Circuitry..................2-24 RTSI Bus Interface Circuitry................2-25 Chapter 3 Register Map and Descriptions Register Map........................3-1 Register Sizes ....................3-3 Register Descriptions .....................3-3 Misc Register Group..................3-3 Serial Command Register ..............3-4 © National Instruments Corporation PCI E Series RLPM...
  • Page 5 Chapter 4 Programming PCl Local Bus........................ 4-1 PCI Initialization for the IBM Compatible System ........4-2 Re-mapping the PCI E Series Board............... 4-3 PCI Initialization for the Macintosh..............4-4 Windowing Registers ....................4-5 Programming Examples ....................4-5 Digital I/O........................4-7 Example 1 .......................
  • Page 6 Interrupt Sharing ......................4-56 DMA Programming .......................4-57 The Link Chaining Mode for DMA Transfer..........4-58 Chapter 5 Calibration About the EEPROM ......................5-1 Calibration DACs ....................5-14 NI-DAQ Calibration Function ..................5-17 Appendix A Customer Communication Glossary Index © National Instruments Corporation PCI E Series RLPM...
  • Page 7 Table 2-2. Analog Input Configuration Memory ..........2-18 Table 3-1. PCI E Series Register Map ..............3-2 Table 3-2. PCI E Series Windowed Register Map ..........3-3 Table 3-3. PGIA Gain Selection................3-10 Table 3-4. Calibration Channel Assignments............3-12 Table 3-5.
  • Page 8 PCI-6033E EEPROM Map ............5-7 Table 5-4. PCI-6023E EEPROM Map ..............5-9 Table 5-5. PCI-6024E and PCI-6025E EEPROM Map .........5-10 Table 5-6. PCI-6052E EEPROM Map ..............5-12 Table 5-7. Type of CALDAC Used on Board ............5-14 © National Instruments Corporation PCI E Series RLPM...

  • Page 9: About This Manual

    Reference Manual. You must use your register-level programmer manual along with the DAQ-STC Technical Reference Manual for a complete understanding of PCI E Series board programming. Unless otherwise noted, text applies to all boards in the PCI E Series. The PCI E Series boards are: •...

  • Page 10: Organization Of This Manual

    • Chapter 3, Register Map and Descriptions, describes in detail the address and function of each of the PCI E Series control and status registers. • Chapter 4, Programming, contains programming instructions for operating the circuitry on the PCI E Series boards.

  • Page 11: Related Documentation

    PC refers to the IBM PC AT and compatible computers with the PCI bus. Related Documentation The following National Instruments manuals contain general information and operating instructions for the PCI E Series boards: • PCI E Series User Manual •...

  • Page 12: General Description

    DAQ boards in your PCI bus computer. The PCI E Series boards can interface to an SCXI system so that you can acquire over 3,000 analog signals from thermocouples, RTDs, strain gauges, voltage sources, and current sources.
  • Page 13 SCXI is the instrumentation front end for plug-in DAQ boards. Your PCI E Series board is completely software configurable. Refer to your PCI E Series User Manual if you have not already installed and configured your board. PCI E Series RLPM...

  • Page 14: Theory Of Operation

    Theory of Operation This chapter contains a functional overview of the PCI E Series boards and explains the operation of each functional unit making up the PCI E Series boards. Functional Overview The block diagram in Figures 2-1 through 2-5 give a functional overview of each PCI E Series board.

  • Page 15: Figure 2-2. Pci-Mio-16Xe-10, Pci-6052E, And Pci-6031E Block Diagram

    DAC0 Data (16) FIFO DAC1 Calibration RTSI Bus DACs * (32) for the PCI-6031E ** (6) for the PCI-6052E *** (8) for the PCI-6052E Figure 2-2. PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E Block Diagram PCI E Series RLPM © National Instruments Corporation...

  • Page 16: Figure 2-3. Pci-6023E, Pci-6024E, And Pci-6025E Block Diagram

    Interface Interface Digital I/O AO Control DAC0 DAC1 Calibration DACs RTSI Connector NOT ON 6023E Analog Output DIO (24) DIO Control 82C55A 6025E Only Figure 2-3. PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram © National Instruments Corporation PCI E Series RLPM...

  • Page 17: Figure 2-4. Pci-6032E And Pci-6033E Block Diagram

    DAQ - STC Control Timing Interface Timing I/O Analog Output RTSI Bus Digital I/O Timing/Control Interface Digital I/O (8) * (32) for the PCI-6033E RTSI Bus Figure 2-4. PCI-6032E and PCI-6033E Block Diagram PCI E Series RLPM © National Instruments Corporation...

  • Page 18: Figure 2-5. Pci-Mio-16Xe-50 Block Diagram

    Data (16) DAC1 Calibration RTSI Bus DACs Figure 2-5. PCI-MIO-16XE-50 Block Diagram The following major components make up the PCI E Series boards: • PCI bus interface circuitry with Plug and Play capability (MITE) • Analog input circuitry • Analog trigger circuitry •...

  • Page 19: Pci Interface Circuitry

    INTA line on the PCI bus interface. Using two interrupt lines, such as INTB, INTC or INTD, is not permitted for the PCI E Series since each function in the PCI E Series does not have its own configuration space. PCI E Series boards have the DAQ-STC IRQOUT0 line connected to the MITE interrupt input.

  • Page 20: Analog Input And Timing Circuitry

    Figure 2-6. PCI Bus Interface Circuitry Block Diagram Analog Input and Timing Circuitry The PCI E Series boards have 16 and 64 analog input channels and a timing core within the DAQ-STC that is dedicated to analog input operation. Figure 2-7 shows a general block diagram for the analog input circuitry.

  • Page 21: Analog Input Circuitry

    *ACH63 for PCI-6071E, PCI-6031E, and PCI-6033E Figure 2-7. Analog Input and Data Acquisition Circuitry Block Diagram Analog Input Circuitry The general model for analog input on the PCI E Series boards includes input multiplexer, multiplexer mode selection switches, a software-programmable gain instrumentation amplifier, calibration hardware, a sampling ADC, a 16-bit wide data FIFO, and a configuration memory.

  • Page 22: Table 2-1. Pgia Gain Set Verses Board

    16 channels. These bits control the input multiplexers. The programmable gain instrumentation amplifier (PGIA) serves two purposes on the PCI E Series boards. The PGIA applies gain to the input signal, amplifying an analog input signal before sampling and conversion to increase measurement resolution and accuracy.
  • Page 23 –32,768 to 32,767 in bipolar mode and 0 to 65,535 in unipolar mode. The PCI E Series boards include a 16-bit wide FIFO to buffer the analog input data. This buffering will increase the maximum rate that the analog input can sustain during continuous acquisition.

  • Page 24: Data Acquisition Timing Circuitry

    You can generate a single conversion in three different ways—apply an active pulse to the CONVERT* pin of the I/O connector, generate a falling edge on the sample-interval counter of the DAQ-STC, or strobe the © National Instruments Corporation 2-11 PCI E Series RLPM...

  • Page 25: Data Acquisition Sequence Timing

    Chapter 2 Theory of Operation appropriate bit in a register in the PCI E Series register set. Any one of these operations will generate the timing shown in Figure 2-8. CONVERT* ADC_BUSY* SHIFTIN* Figure 2-8. ADC Timing When SHIFTIN* shifts the ADC value into the ADC FIFO buffer, the AI_FIFO_Empty_St bit in the status register is cleared, which indicates that valid data is available to be read.
  • Page 26 10 µs, program your configuration memory as follows: Channel 0, gain 50 Channel 5, gain 2 Channel 3, gain 10, last channel You should program SI2 for 10 µs, SI for 100 µs, and SC for 50 scans. © National Instruments Corporation 2-13 PCI E Series RLPM...

  • Page 27: Figure 2-9. Timing Of Scan In Example 1

    Example 2: To sample channel 0 at 10 kS/s and channel 1 at 5 kS/s, both at gain 1 with 50 scans, program the configuration memory as follows: Channel 0, gain 1 Channel 1, gain 1, last channel Channel 0, gain 1, last channel PCI E Series RLPM 2-14 © National Instruments Corporation...

  • Page 28: Figure 2-10. Multirate Scanning Of Two Channels

    CONVERT pulses indicate the channels sampled in that conversion. Sampling Rates Channel 0: Channel 1 = 5:1 START CONVERT STOP Figure 2-11. Multirate Scanning of Two Channels with 1: x Sampling Rate © National Instruments Corporation 2-15 PCI E Series RLPM...

  • Page 29: Figure 2-12. Multirate Scanning Of Two Channels With 3:1:1 Sampling Rate

    Figures 2-14 and 2-16 illustrate the advantages of using the ghost feature. Figure 2-15 shows Example 3 timing, and Figure 2-16 shows the same example using ghost. Example 3: channel 1: channel 0 = 2:3 (without ghost). PCI E Series RLPM 2-16 © National Instruments Corporation...

  • Page 30: Figure 2-14. Multirate Scanning Without Ghost

    Figure 2-16. Successive Scans Using Ghost The shaded conversions are ghost conversions. The short arrows indicate channel 0 samples and the long arrows indicate channel 1 samples that are actually stored in the FIFOs. © National Instruments Corporation 2-17 PCI E Series RLPM...

  • Page 31: Posttrigger And Pretrigger Acquisition

    SCAN counter counts down to zero. In the pretrigger mode, data is acquired before and after the trigger. In this mode, both START1 and START2 lines are used. There are two counts for PCI E Series RLPM 2-18 © National Instruments Corporation...

  • Page 32: Analog Triggering

    SC. When the SC counts down to zero, acquisition stops. Analog Triggering All PCI E Series boards except the PCI-MIO-16XE-50, PCI-6023E, PCI-6024E, and PCI-6025E have an analog trigger in addition to the digital triggers. To use analog triggering to start an acquisition sequence, select either the PFI0/Trig1 input on the I/O connector or one of the analog input pins.

  • Page 33: Analog Output And Timing Circuitry

    Technical Reference Manual. Analog Output and Timing Circuitry The PCI E Series boards (except the PCI-6023E, PCI-6032E and PCI-6033E) have two analog output channels and a timing core within the DAQ-STC that is dedicated to analog output operation. Figure 2-17 shows a general block diagram for the analog output circuitry.

  • Page 34: Analog Output Circuitry

    FIFO to buffer the data. However, not all of the PCI E Series boards contain every one of these features. Each analog output channel contains a 12-bit DAC, an amplification stage, and an onboard voltage reference, except for the PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E, which have a 16-bit DAC.

  • Page 35: Analog Output Timing Circuitry

    DC levels, where precise timing of the output change is not important. Writing directly to the DACs is accomplished by writing the desired value to the DAC<0..1> Direct Data PCI E Series RLPM 2-22 © National Instruments Corporation...

  • Page 36: Waveform Generation

    The large FIFOs can also be used to generate repetitive waveforms at very high speeds and without using any bus bandwidth. The FIFOs can be loaded with the desired waveform and the DAQ-STC can be programmed © National Instruments Corporation 2-23 PCI E Series RLPM...

  • Page 37: Digital I/O Circuitry

    DAC. Digital I/O Circuitry The PCI E Series boards have eight digital I/O lines. Each of the eight digital lines can be individually programmed to be input or output, if used in parallel.

  • Page 38: Rtsi Bus Interface Circuitry

    UPDOWN pin determines the direction of counting. Active polarities of these pins are software selectable in the DAQ-STC. Notice that on the PCI E Series boards only the SOURCE, GATE, and OUT pins are brought out to the I/O connector. The UPDOWN pin for counter 0 is internally connected to DIO6, and to DIO7 for counter 1.

  • Page 39: Figure 2-19. Rtsi Bus Interface Circuitry Block Diagram

    Of the four RTSI board signals, only one is used. By programming certain bits in the DAQ-STC, you can drive the CONVERT pulse onto RTSI_BRD0 and then onto any of the TRIGGER lines. PCI E Series RLPM 2-26 © National Instruments Corporation...

  • Page 40: Register Map And Descriptions

    PCI E Series board by reading this chapter. Register Map Table 3-1 shows the register map for the PCI E Series boards and gives the register name, the register offset address, the type of the register (read-only, write-only, or read-and-write), and the size of the register in bits.

  • Page 41: Table 3-1. Pci E Series Register Map

    Chapter 3 Register Map and Descriptions Table 3-1. PCI E Series Register Map Offset Address Register Name Decimal Type Size Misc Register Group Serial Command Write-only 8-bit Misc Command Write-only 8-bit Status Read-only 8-bit Analog Input Register Group ADC FIFO Data Register...

  • Page 42: Register Sizes

    Register Descriptions This section discusses each of the PCI E Series registers in the order shown in Table 3-1. Each register group is introduced, followed by a detailed bit description. The individual register description gives the address, type, word size, and bit map of the register, followed by a description of each bit.

  • Page 43: Serial Command Register

    Chapter 3 Register Map and Descriptions Serial Command Register The Serial Command Register contains six bits that control PCI E Series serial EEPROM and DACs. The contents of this register are cleared upon power up and after a reset condition. Address:...

  • Page 44: Misc Command Register

    Chapter 3 Register Map and Descriptions Misc Command Register The Misc Command Register contains one bit that controls the PCI E Series analog trigger source. The contents of this register are cleared upon power up and after a reset condition. Address:...

  • Page 45: Status Register

    8-bit Bit Map: Reserved Reserved Reserved Reserved Reserved Reserved Reserved PROMOUT Name Description 7–1 Reserved Reserved—Ignore returned bits. PROMOUT EEPROM Output Data—This bit reflects the serial output data of the serial EEPROM. PCI E Series RLPM © National Instruments Corporation...

  • Page 46: Analog Input Register Group

    ADC FIFO contents. Reading the ADC FIFO Data Register location transfers data from the PCI E Series ADC data FIFO to the computer. Writing to the Configuration Memory Low and Configuration Memory High Register locations sets up channel configuration information for the analog input section.

  • Page 47: Adc Fifo Data Register

    ADC is in unipolar mode and 32,768 to 32,767 decimal (0x8000 to 0x7FFF) when the ADC is in bipolar mode. The mode is controlled by the Unip/Bip bit in the Configuration Memory Low Register. PCI E Series RLPM © National Instruments Corporation...

  • Page 48: Configuration Memory Low Register

    Dither Enable—This bit controls the dither circuitry feeding the analog input. If this bit is set, approximately ±0.5 LSB of white Gaussian noise is added to the input signal. This bit is reserved on the PCI-MIO-16XE-50, © National Instruments Corporation PCI E Series RLPM...

  • Page 49: Table 3-3. Pgia Gain Selection

    Channel Gain Select 2 through 0—These three bits control the gain settings of the input PGIA for the selected analog channel. The gains shown in Table 3-3 can be selected on the PCI E Series boards. Table 3-3. PGIA Gain Selection Gain<2..0>...

  • Page 50: Configuration Memory High Register

    ChanType<2..0> Channel Type 2 through 0—These bits indicate which type of resource is active for the current entry in the scan list. The following table lists the valid channel types. Chan Type<2..0> Resource Calibration Differential NRSE Ghost © National Instruments Corporation 3-11 PCI E Series RLPM...

  • Page 51: Table 3-4. Calibration Channel Assignments

    Not every resource uses all 16 channels in a bank. Channel assignments for all PCI E Series or higher boards follow. Table 3-4. Calibration Channel Assignments Chan Type<2..0> = CAL Chan<3..0>...

  • Page 52: Table 3-5. Differential Channel Assignments

    AISense 0010 ACh2 AISense 0011 ACh3 AISense 0100 ACh4 AISense 0101 ACh5 AISense 0110 ACh6 AISense 0111 ACh7 AISense 1000 ACh8 AISense 1001 ACh9 AISense 1010 ACh10 AISense 1011 ACh11 AISense © National Instruments Corporation 3-13 PCI E Series RLPM...

  • Page 53: Table 3-7. Referenced Single-Ended Channel Assignments

    AIGround 0110 ACh6 AIGround 0111 ACh7 AIGround 1000 ACh8 AIGround 1001 ACh9 AIGround 1010 ACh10 AIGround 1011 ACh11 AIGround 1100 ACh12 AIGround 1001 ACh13 AIGround 1110 ACh14 AIGround 1111 ACh15 AIGround PCI E Series RLPM 3-14 © National Instruments Corporation...

  • Page 54: Analog Output Register Group

    DACs in one of two ways. Data can be directly sent to the DACs from the host computer, or buffered from the host by the DAC data FIFO. © National Instruments Corporation 3-15 PCI E Series RLPM...

  • Page 55: Ao Configuration Register

    Chapter 3 Register Map and Descriptions AO Configuration Register The AO Configuration Register contains five bits that control the PCI E Series analog output configuration. The contents of this register are cleared upon power up and after a reset condition.
  • Page 56 DAC is interpreted in straight binary format. This bit is reserved on the PCI-MIO-16XE-50 and should be set to 1. The PCI-MIO-16XE-50, PCI-6024E, and PCI-6025E DACs are always configured in bipolar mode. © National Instruments Corporation 3-17 PCI E Series RLPM...

  • Page 57: Dac Fifo Data Register

    In bipolar mode, the valid range is –32,768 to 32,767 for a 16-bit DAC and –2,048 to 2,047 for a 12-bit DAC. PCI E Series RLPM 3-18 © National Instruments Corporation...

  • Page 58: Dac0 Direct Data Register

    In bipolar mode, the valid range is –32,768 to 32,767 for a 16-bit DAC and –2,048 to 2,047 for a 12-bit DAC. © National Instruments Corporation 3-19 PCI E Series RLPM...

  • Page 59: Dac1 Direct Data Register

    In bipolar mode, the valid range is –32,768 to 32,767 for a 16-bit DAC and –2,048 to 2,047 for a 12-bit DAC. PCI E Series RLPM 3-20 © National Instruments Corporation...

  • Page 60: Dma Control Register Group

    Register Map and Descriptions DMA Control Register Group The two registers making up the DMA Control Register Group configure the PCI E Series boards DMA interface. The AI AO Select and G0 G1 Select Registers select the DMA channels for the analog input, analog output, and general purpose counter timer resources.

  • Page 61: Ai Ao Select Register

    Analog Input Logical Channel D through A—These four bits select the logical channels to be used by the analog input. You can only set one of these bits at a time. PCI E Series RLPM 3-22 © National Instruments Corporation...

  • Page 62: G0 G1 Select Register

    GPCT0 <D..A> General Purpose Counter Timer 0 Logical Channel C through A—These four bits select the MITE logical channels that the GPCT1 uses. You can only set one of these bits at a time. © National Instruments Corporation 3-23 PCI E Series RLPM...

  • Page 63: Daq-Stc Register Group

    FIFO Strobe Register Group The three registers making up the FIFO Strobe Register Group are used to clear the three FIFOs on the PCI E Series. Configuration Memory Clear Register Accessing the Configuration Memory Clear Register clears all information in the channel configuration memory and resets the write pointer to the first location in the memory.

  • Page 64: Programming

    Companion Disk. PCl Local Bus The PCI E Series boards are fully compatible with the PCI Local Bus Specification, Version 2.1 from the PCI Special Interest Group (SIG). The PCI Local Bus is a high performance, 32-bit bus with multiplexed address and data lines.

  • Page 65: Pci Initialization For The Ibm Compatible System

    . This verifies that the PCI bus is present. It scans the PCI bus for all National Instruments PCI E Series boards using Find_NI_Devices() function. PCI BIOS calls are again used to find PCI boards that contain the National Instruments Vendor ID (0x1093) and a valid PCI E Series device ID (for example the device ID of the PCI-MIO-16XE-50 is 0x0162).

  • Page 66: Re-Mapping The Pci E Series Board

    Programming Re-mapping the PCI E Series Board The PCI E Series board uses two base address registers (BAR). BAR points to the base address for the MITE registers, while BAR1 points to the base address of the board registers such as the DAQ-STC.

  • Page 67: Pci Initialization For The Macintosh

    PCI boards that contain the National Instruments vendor ID (0x1093) and PCI E Series board ID (for example, the board ID for the PCI-MIO-16XE-50 is 0x0162) in their configuration space. If a board is found, the program stores pertinent information of the board into a data structure.

  • Page 68: Windowing Registers

    In addition to the DAQ-STC registers, the PCI E Series boards have other discrete registers. In order to retain compatibility with the AT E Series boards, which have a limited address space, the PCI E Series boards use the same windowing scheme for the DAQ-STC.
  • Page 69 Please refer to Chapter 2, Register and Bitfield Programming Considerations, in the DAQ-STC Technical Reference Manual for further information. PCI E Series RLPM © National Instruments Corporation...

  • Page 70: Digital I/O

    Companion Disk. Configure lines 0, 2, 4, and 6 as outputs and 1, 3, 5, and 7 as inputs. DIO_Control_Register = 0x55; Write the digital pattern. DIO_Output_Register = 0x00; © National Instruments Corporation PCI E Series RLPM...

  • Page 71: Analog Input

    Individual bitfield descriptions are also provided. Programming the PCI E Series boards for analog input can be divided into writing to and reading from two main register groups: discrete board registers and DAQ-STC registers. The following functions configure the...

  • Page 72: Example 1

    Chapter 4 Programming pseudo-code for each example. The PCI E Series Register Level Programmer Manual Companion Disk contains the complete programs. The following pseudo-code examples and the programs on the Companion Disk follow the flowchart structure presented in the DAQ-STC Technical Reference Manual.
  • Page 73 AI_Mode_1_Register Reserved one = 1; AI start stop = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; sets the DAQ-STC for the PCI E Series AI_Board_Personalize board. Joint_Reset_Register AI configuration start = 1; Clock_and_FOUT_Register Output divide by two = 1;...
  • Page 74 AI_End_of_Scan Joint_Reset_Register AI configuration start = 1; AI_Start_Stop_Select_Register Stop select = 19; Stop sync = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; © National Instruments Corporation 4-11 PCI E Series RLPM...

  • Page 75: Example 2

    AI configuration start = 1; AI_SC_Load_A_Registers (24 bits) Number of posttrigger scans -1 = 4; AI_Command_1_Register AI SC Load = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; PCI E Series RLPM 4-12 © National Instruments Corporation...
  • Page 76 AI SI2 load = 1; AI_Mode_2_Register AI SI2 initial load source = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; Perform Analog Input Example 1 Step 4. © National Instruments Corporation 4-13 PCI E Series RLPM...

  • Page 77: Example 3

    Use the OS specific functions such as getvect() setvect() DOS to replace the default interrupt handler with your ISR. You should disable interrupts during this step. Reset the interrupt controller hardware. PCI E Series RLPM 4-14 © National Instruments Corporation...

  • Page 78: Example Program

    AI SI load = 1; AI_SI_Load_A_Registers (24 bits) AI SI ordinary ticks -1 = 19999; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; Perform Analog Input Example 1 Step 11. © National Instruments Corporation 4-15 PCI E Series RLPM...
  • Page 79 AI SI arm = 1; AI SI2 arm = 1; AI DIV arm = 1; 11. Install the interrupt service routine to handle the interrupt. Interrupt_Service_Routine() read FIFO data; increment sample counter; PCI E Series RLPM 4-16 © National Instruments Corporation...

  • Page 80: Example 4

    Perform Analog Input Example 1 Step 1. Perform Analog Input Example 1 Step 2 for each channel in the scan list. Only channel 0 has Last channel set to 1. Perform Analog Input Example 1 Steps 3-9. © National Instruments Corporation 4-17 PCI E Series RLPM...
  • Page 81 AI configuration start = 1; AI_SI2_Load_A_Register AI SI2 special ticks -1 = 1999; AI_SI2_Load_B_Register AI SI2 ordinary ticks -1 = 1999; AI_Mode_2_Register AI SI2 reload mode = 1; AI_Command_1_Register AI SI2 load = 1; PCI E Series RLPM 4-18 © National Instruments Corporation...
  • Page 82 Your DMA transfer direction (INPUT or OUTPUT) continuous: Perform continuous DMA transfer (FALSE or TRUE) drqnum: DRQ channel you want to use. Make sure it is the same in Step 11 (0 to 3). © National Instruments Corporation 4-19 PCI E Series RLPM...

  • Page 83: Programming The Mite For Different Dma Transfers

    1 for drqnum, OUTPUT for direction, FALSE for continuous and 1 for dmachannel. Then call twice for DMA channel 0 and channel 1. After the DMA MITE_DMAarm PCI E Series RLPM 4-20 © National Instruments Corporation...

  • Page 84: Example 5

    AI_Command_1_Register AI SC Load = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; The function selects the scan start event. AI_Scan_Start Joint_Reset_Register AI configuration start = 1; © National Instruments Corporation 4-21 PCI E Series RLPM...
  • Page 85 11. Poll the AI FIFO not empty flag in the AI_Status_1_Register until not empty and read the ADC FIFO data in the ADC_FIFO_Data_Register. If (AI FIFO not empty) then read FIFO data; } while (20 samples have not been read) PCI E Series RLPM 4-22 © National Instruments Corporation...

  • Page 86: Example 6

    Number of pretrigger scans -1 = 9; AI_Mode_2_Register AI SC initial load source = 1; AI SC reload mode = 1; AI_SC_Load_A_Registers (24 bits) Number of posttrigger scans -1 = 9; AI_Command_1_Register AI SC load = 1; © National Instruments Corporation 4-23 PCI E Series RLPM...
  • Page 87 AI SI2 load = 1; AI_Mode_2_Register AI SI2 initial load source = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; Perform Analog Input Example 1 Step 4. PCI E Series RLPM 4-24 © National Instruments Corporation...

  • Page 88: Example 7

    AI configuration start = 1; AI_SC_Load_A_Registers (24 bits) Number of posttrigger scans -1 = 4; AI_Command_1_Register AI SC Load = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; © National Instruments Corporation 4-25 PCI E Series RLPM...
  • Page 89 11. Poll the AI FIFO not empty flag in the AI_Status_1_Register until not empty and read the ADC FIFO data in the ADC_FIFO_Data_Register. If (AI FIFO not empty) then read FIFO data; } while (20 samples have not been read) PCI E Series RLPM 4-26 © National Instruments Corporation...

  • Page 90: Example 8

    AI SC Load = 1; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; The function selects the scan start event. AI_Scan_Start Joint_Reset_Register AI configuration start = 1; AI_START_STOP_Select_Register = 0x0060; © National Instruments Corporation 4-27 PCI E Series RLPM...
  • Page 91 AI SC arm = 1; AI SI arm = 1; AI SI2 arm = 1; AI DIV arm = 1; 12. Now start the acquisition with AI_Start_The_Acquisition AI_Command_2_Register AI START1 pulse = 1; PCI E Series RLPM 4-28 © National Instruments Corporation...

  • Page 92: Example 9

    DIO_Control_Register = 0x0000; DIO_Output_Register = 0x0000; DIO_Control_Register = 0x0003; DIO_Control_Register = 0x0803; DIO_Control_Register = 0x0003; The function configures the board AI_Board_Environmentalize for any external multiplexers. Joint_Reset_Register AI configuration start = 1; © National Instruments Corporation 4-29 PCI E Series RLPM...
  • Page 93 AI SI load = 1; AI_SI_Load_A_Registers (24 bits) AI AI ordinary ticks - 1 = 3999; Joint_Reset_Register AI configuration start = 0; AI configuration end = 1; Perform Analog Input Example 1 Step 11. PCI E Series RLPM 4-30 © National Instruments Corporation...

  • Page 94: Analog Output

    } while (80 samples have not been read) Analog Output Chapter 3 of the DAQ-STC Technical Reference Manual contains all the information on the analog output timing/control module of the DAQ-STC, © National Instruments Corporation 4-31 PCI E Series RLPM...

  • Page 95: Example 1

    Example 1. This manual provides the structure and pseudo-code for each example. The PCI E Series Register Level Programmer Manual Companion Disk contains the complete programs. The following pseudo-code examples and the programs on the Companion Disk follow the flowchart structure presented in the DAQ-STC Technical Reference Manual.
  • Page 96 AO_START_Select_Register = 0x 0000; Joint_Reset_Register AO configuration start = 0; AO configuration end = 1; Call to set the update mode AO_LDAC_Source_And_Update_Mode to immediate update mode. Joint_Reset_Register AO configuration start = 1; © National Instruments Corporation 4-33 PCI E Series RLPM...

  • Page 97: Example 2

    GroundRef = 0; Reset the data FIFO. Pre-load the data FIFO with the voltages from the array. while (FIFO is not full and there is more data to write) AO_DAC_FIFO_Data = data; PCI E Series RLPM 4-34 © National Instruments Corporation...
  • Page 98 Call to program the trigger signal. Configure the AO_Triggering DAQ-STC to trigger once and use a software START1 trigger. Joint_Reset_Register AO configuration start = 1; AO_Mode_1_Register AO trigger once = 1; © National Instruments Corporation 4-35 PCI E Series RLPM...
  • Page 99 AO configuration start = 0; AO configuration end = 1; 11. Call to program the update interval. Use the internal AO_Updating UPDATE mode. Set the UI source to AO_IN_TIMEBASE1. Load the PCI E Series RLPM 4-36 © National Instruments Corporation...
  • Page 100 AO_Channels Joint_Reset_Register AO configuration start = 1; AO_Mode_1_Register AO multiple channels = 0; AO_Output_Control_Register AO number of channels = 1; Joint_Reset_Register AO configuration start = 0; AO configuration end = 1; © National Instruments Corporation 4-37 PCI E Series RLPM...
  • Page 101 17. Call to arm the counters and preload the DAC with the AO_Arming first analog output value. AO_Mode_3_Register AO not an UPDATE = 1; AO_Mode_3_Register AO not an UPDATE = 0; PCI E Series RLPM 4-38 © National Instruments Corporation...

  • Page 102: Example 2

    100 points). Joint_Reset_Register AO configuration start = 1; AO_Mode_1_Register AO continuous = 0; AO_Mode_2_Register AO BC initial load source = 0; AO_BC_Load_A_Registers (24 bits) Number of buffers -1 = 49; © National Instruments Corporation 4-39 PCI E Series RLPM...
  • Page 103 AO UI special ticks -1 = 1; AO_Command_1_Register AO UI load = 1; AO_UI_Load_A_Registers (24 bits) AO UI ordinary ticks - 1 = 1999; Joint_Reset_Register AO configuration start = 0; AO configuration end = 1; PCI E Series RLPM 4-40 © National Instruments Corporation...

  • Page 104: Example 3

    Perform Analog Output Example 2 Steps 1 through 8. Call to program the trigger signal. Configure the AO_Triggering DAQ-STC to trigger once. Set the START1 select to PFI6. Joint_Reset_Register AO configuration start = 1; © National Instruments Corporation 4-41 PCI E Series RLPM...
  • Page 105 Points per buffer = 100; AO_Command_1_Register AO UC load = 1; AO_UC_Load_A_Registers (24 bits) Points per buffer - 1 = 99; Joint_Reset_Register AO configuration start = 0; AO configuration end = 1; PCI E Series RLPM 4-42 © National Instruments Corporation...

  • Page 106: Example Program

    Perform Analog Output Example 2 Steps 1 through 14. Call to disable the FIFO retransmit and set the FIFO mode. AO_FIFO Joint_Reset_Register AO configuration start = 1; AO_Mode_2_Register AO FIFO Mode = 1; AO FIFO retransmit enable = 0; © National Instruments Corporation 4-43 PCI E Series RLPM...
  • Page 107 AO_Command_2_Register AO START1 pulse = 1; Poll the AO FIFO half full flag in the AO_Status_1_Register until half full and call the ISR. If (AO FIFO half full) then call service_interrupt; PCI E Series RLPM 4-44 © National Instruments Corporation...

  • Page 108: General-Purpose Counter/Timer

    Companion Disk. Call to set all the PFI pins for input. MSC_IO_Pin_Configure() IO_Bidirection_Pin_Register BD_i_Pin_Dir <= 0; Call to reset all the necessary registers in G0_Reset_All() DAQ-STC. Joint Reset Register G0_Reset=1; © National Instruments Corporation 4-45 PCI E Series RLPM...
  • Page 109 G0_Loading_On_Gate = 0; G0_Loading_On_TC = 0; GO_Gating_Mode = 1; G0_Gate_On_Both_Edges = 0; GO_Trigger_Mode_For_Edge_Gate = 2; G0_Stop_Mode = 0; G0_Counting_Once = 0; G0_Command_Register G0_Up_Down = 1; (up counting) G0_Bank_Switch_Enable = 0; G0_Bank_Switch_Mode = 0; PCI E Series RLPM 4-46 © National Instruments Corporation...

  • Page 110: Example 2

    Example 3 in the Analog Input section. Perform General Purpose Counter and Timer Example 1 Step 1 through 3. to set up the Call Buffered_Pulse_Width_Measurement() DAQ-STC for buffered pulse width measurement. Go_Mode_Register G0_Load_Source=0; © National Instruments Corporation 4-47 PCI E Series RLPM...
  • Page 111 G0_Bank_Switch_Mode = 0; Interrupt_A_Enable_Register G0_TC_Interrupt_Enable = 0; G0_Gate_Interrupt_Enable = 1; Call to begin the operation. G0_Arm() G0_Command_Register G0_Arm=1; performs the reading from Pulse_Width_Measurement_ISR() HW_Save Register. save_1=G0_HW_Registers (24 bits); if (G0_Stale_Data_St==1) then save_1=0; PCI E Series RLPM 4-48 © National Instruments Corporation...

  • Page 112: Example 3

    It generates continuous pulses on the pin with a three clock delay G_Out from the trigger, pulse interval of four clocks, and pulsewidth of three clocks. (20 MHz) is . The waveform G_in_timebase G_source © National Instruments Corporation 4-49 PCI E Series RLPM...
  • Page 113 G0_Load=1; G0_Load_A_Registers (24 bits) G0_Load_A=0x0003; //pulse interval -1 G0_Load_B_Registers (24 bits) G0_Load_B=0x0002; //pulse width -1 G0_Mode_Register G0_Load_Source_Select=1; G0_Input_Select_Register G0_Source_Select=0; (G_In_TimeBase) G0_Source_Polarity=0; (rising edges) G0_Gate_Select=5; (PFI4) G0_OR_Gate=0; G0_Output_Polarity=0; (active high) G0_Gate_Select_Load_Source=0; G0_Mode_register PCI E Series RLPM 4-50 © National Instruments Corporation...
  • Page 114 ((G0_Bank_St==1)==g_bank_to_be_used) then G0_Load_A_Register (24 bits) G0_Load_A <= pulse interval -1 (3) G0_Load_B_Register G0_Load_B <= pulsewidth -1 (3) © National Instruments Corporation 4-51 PCI E Series RLPM...

  • Page 115: Rtsi Trigger Lines Programming Considerations

    Analog Triggering All of the PCI E Series boards except the PCI-MIO-16XE-50, PCI-6023E, PCI-6024E, and PCI-6025E contain true analog triggering hardware, which provides fast slope and level detection, as well as window detection.
  • Page 116 See the DAQ-STC Technical Reference Manual for their appropriate use. Figure 4-1 shows the analog trigger structure. When writing to CALDAC 11, also write the same value to CALDAC 0. © National Instruments Corporation 4-53 PCI E Series RLPM...

  • Page 117: Figure 4-1. Analog Trigger Structure

    8-bit and 12-bit DACs is illustrated in Chapter 5 of this manual in the Calibration DACs section. The example uses low-hysteresis mode and the PGIA as the triggering source. The low value is set to be 0 V, PCI E Series RLPM 4-54 © National Instruments Corporation...
  • Page 118 AI configuration end=1; Perform Steps 5 through 8 in Analog Input Example 2. Call the Analog Trigger Control Analog_Trigger_Etc_Register Analog_Trigger_Mode =6 (low hysteresis); Analog_Trigger_Drive=0; Analog_Trigger_Enable=1(Enable); Mis_Command_Register (8 bits) Int/Ext Trigger =1 (PGIA2) © National Instruments Corporation 4-55 PCI E Series RLPM...

  • Page 119: Interrupt Programming

    }while (100 samples have not been read) Interrupt Programming Chapter 8, Interrupt Control, in the DAQ-STC Technical Reference Manual, discusses the interrupt programming aspect of the PCI E Series boards. There are two groups—Interrupt Group A and Interrupt Group B. Group A handles the analog input interrupts, general-purpose Counter 0 interrupts, and one pass-through interrupt.

  • Page 120: Dma Programming

    If it does not, the ISR must pass control to the next ISR in the chain. In order to determine if a PCI E Series board has a pending interrupt do the following: Perform a 32 bit memory read from BAR0 + 0x14.

  • Page 121: The Link Chaining Mode For Dma Transfer

    DMA transfers on different memory segments and makes seamless data transfer possible. Inside the linked list structure, each node contains values for TCR, MAR, DAR, and LKAR. TCR (Transfer Count Register) stores the total number PCI E Series RLPM 4-58 © National Instruments Corporation...

  • Page 122: Figure 4-3. Dma Link Chaining Mode Structure

    Buffer 0 Use Physical Address Use Physical Address LKAR Use Physical Address LKAR Use Physical Address Buffer 1 Use Physical Address LKAR 0 (Last Link) Figure 4-3. DMA Link Chaining Mode Structure © National Instruments Corporation 4-59 PCI E Series RLPM...

  • Page 123: Calibration

    Calibration This chapter explains how to calibrate the analog input and output sections of the PCI E Series boards by reading calibration constants from the EEPROM and writing them to the calibration DACs. This chapter also explains how to generate the calibration constants using NI-DAQ.

  • Page 124: Figure 5-1. Eeprom Read Timing

    Do not attempt to write to the EEPROM. If the factory area of the EEPROM (the upper 128 bytes) is lost, the board can be rendered inoperable. In this situation, you will have to send the board back to National Instruments to be reprogrammed. National Instruments is liable for such mistakes, and you will have to bear the full expense of the RMA.

  • Page 125: Table 5-1. Pci-Mio-16E-1, Pci-Mio-16E-4, Pci-6071E Eeprom Map

    (8-bit) CALDAC factory constant Bipolar AO MB88341 7 and 13 (8-bit) CALDAC factory constant Bipolar AO MB88341 (8-bit) CALDAC factory constant Bipolar AO MB88341 (8-bit) CALDAC factory constant Bipolar AO MB88341 (8-bit) © National Instruments Corporation PCI E Series RLPM...
  • Page 126 MB88341 (8-bit) Factory calibration — — — — temperature Start of the five user — — — — calibration sections Board Codes: 205—PCI-MIO-16E-1 206—PCI-MIO-16E-4 207—PCI-6071E Write both CALDAC addresses for these constants PCI E Series RLPM © National Instruments Corporation...

  • Page 127: Table 5-2. Pci-Mio-16Xe-50 Eeprom Map

    8800 (8-bit) CALDAC factory constant Unipolar AI DAC8043 — (12-bit) CALDAC factory constant Unipolar AI DAC8043 — (12-bit) CALDAC factory constant Unipolar AI 8800 (8-bit) CALDAC factory constant Unipolar AI 8800 (8-bit) © National Instruments Corporation PCI E Series RLPM...
  • Page 128 CALDAC factory constant 8800 (8-bit) CALDAC factory constant 8800 (8-bit) CALDAC factory constant 8800 (8-bit) Factory calibration — — — — temperature Start of the five user — — — — calibration sections PCI E Series RLPM © National Instruments Corporation...

  • Page 129: Table 5-3. Pci-Mio-16Xe-10, Pci-6031E, Pci-6032E And Pci-6033E Eeprom Map

    8800 (8-bit) CALDAC factory constant Bipolar AI 8800 (8-bit) CALDAC factory constant Unipolar AI DAC8043 — (12-bit) CALDAC factory constant Unipolar AI DAC8043 — (12-bit) CALDAC factory constant Unipolar AI 8800 (8-bit) © National Instruments Corporation PCI E Series RLPM...
  • Page 130 8800 (8-bit) CALDAC factory constant Unipolar 8800 (8-bit) Factory calibration — — — — temperature Start of the five user — — — — calibration sections Board Codes: 204—PCI-MIO-16XE-10 220—PCI-6031E 221—PCI-6032E 222—PCI-6033E PCI E Series RLPM © National Instruments Corporation...

  • Page 131: Table 5-4. Pci-6023E Eeprom Map

    — — — temperature Start of the five user — — — — calibration sections (MSB × 256) + LSB = Board Code Board Codes (1 × 256) + 11 = 267 © National Instruments Corporation PCI E Series RLPM...

  • Page 132: Table 5-5. Pci-6024E And Pci-6025E Eeprom Map

    Bipolar AI MB88341 (8-bit) CALDAC factory constant Bipolar AO MB88341 (8-bit) CALDAC factory constant Bipolar AO MB88341 (8-bit) CALDAC factory constant Bipolar AO MB88341 (8-bit) CALDAC factory constant Bipolar AO MB88341 (8-bit) PCI E Series RLPM 5-10 © National Instruments Corporation...
  • Page 133 (MSB × 256) + LSB = Board Code Board Codes LSB (1 × 256) + 13 = 269 13—PCI-6024E (1 × 256) + 15 = 271 15—PCI-6025E Board Codes MSB: 01—PCI-6024E 01—PCI-6025E © National Instruments Corporation 5-11 PCI E Series RLPM...

  • Page 134: Table 5-6. Pci-6052E Eeprom Map

    CALDAC factory constant AI gain MB88341 coarse CALDAC factory constant AI gain fine MB88341 CALDAC factory constant AI unipolar MB88341 offset coarse CALDAC factory constant AI unipolar MB88341 offset fine PCI E Series RLPM 5-12 © National Instruments Corporation...
  • Page 135 AO 0 MB88341 unipolar linearity CALDAC factory constant AO 0 MB88341 unipolar gain coarse CALDAC factory constant AO 0 MB88341 unipolar gain fine CALDAC factory constant AO 0 MB88341 unipolar offset © National Instruments Corporation 5-13 PCI E Series RLPM...

  • Page 136: Calibration Dacs

    Table 5-7. Type of CALDAC Used on Board MB88341 DAC8800 DAC8043 AD8522 Board (8-bit) (8-bit) (12-bit) (12-bit) PCI-MIO-16E-1 — — — PCI-MIO-16E-4 — — — PCI-6071E — — — PCI-MIO-16XE-50 — — PCI-MIO-16XE-10 — PCI E Series RLPM 5-14 © National Instruments Corporation...
  • Page 137 In other words, when setting the clock bit low, you must write 0 twice, and when setting it high, you must write 1 twice. Note Review the timing diagram and specifications very carefully before attempting to write code. © National Instruments Corporation 5-15 PCI E Series RLPM...

  • Page 138: Figure 5-2. Calibration Ac Write Timing

    D8 D7 D6 D4 D3 SerDacLd d) AD 8522 DACB DACA Figure 5-2. Calibration AC Write Timing Note Refer to the EEPROM Map table of your board for use with Figure 5-2. PCI E Series RLPM 5-16 © National Instruments Corporation...

  • Page 139: Ni-Daq Calibration Function

    The NI-DAQ function called can calibrate the Calibrate_E_Series analog input, analog output, and internal reference on the PCI E Series boards. Due to the complexity of the actual calibration algorithm, use to calibrate each section and store the results Calibrate_E_Series in the EEPROM.

  • Page 140: Appendix A Customer Communication

    Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24-hour support with a collection of files and documents to answer most common customer questions. From these sites, you can also download the latest instrument drivers, updates, and example programs. For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information, call 512 795 6990.
  • Page 141 Telephone and Fax Support National Instruments has branch offices all over the world. Use the list below to find the technical support number for your country. If there is no National Instruments office in your country, contact the source from which you purchased your software to obtain support.
  • Page 142 National Instruments for technical support helps our applications engineers answer your questions more efficiently. If you are using any National Instruments hardware or software products related to this problem, include the configuration forms from their user manuals. Include additional pages if necessary.
  • Page 143 Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
  • Page 144 Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: PCI E Series Register-Level Programmer Manual Edition Date: November 1998 Part Number: 341079B-01 Please comment on the completeness, clarity, and organization of the manual.

  • Page 145: Glossary

    Symbols inverted bit (negative logic) if after a bit name Ω ohms amperes analog-to-digital alternating current A/D converter AIGND analog input ground signal AOGND analog output ground signal ASIC application-specific integrated circuit © National Instruments Corporation PCI E Series RLPM...
  • Page 146 D/A converter DAC0OUT analog channel 0 output signal DAC1OUT analog channel 1 output signal DACSe DAC select bit data acquisition Device Address Register direct current DitherEn dither enable bit PCI E Series RLPM © National Instruments Corporation...
  • Page 147 FIFO first-in-first-out Gain channel gain select bit GenTrig general trigger bit ghost a conversion that is performed but the data is thrown away GPCT0 general-purpose counter timer 0 bit © National Instruments Corporation PCI E Series RLPM...
  • Page 148 Int/Ext Trig internal/external analog trigger interrupt request signal Industry Standard Architecture interrupt service routine LASTCHANNEL last channel bit LKAR Link Address Register least significant bit meters Memory Address Register megabytes of memory PCI E Series RLPM © National Instruments Corporation...
  • Page 149 PFI 1/Trigger 2 signal PGIA Programmable Gain Instrumentation Amplifier parts per million PRETRIG pretrigger signal PROMOUT EEPROM output data bit ReGlitch reglitch DAC bit resistance-temperature detector RTSI Real-Time System Integration bus RTSI_BRD0 RTSI board © National Instruments Corporation PCI E Series RLPM...
  • Page 150 START start signal STOP stop signal terminal count TCIntEnable DMATC interrupt enable bit Transfer Count Register Transfer transfer type bit transistor-transistor logic update counter update interval PCI E Series RLPM © National Instruments Corporation...
  • Page 151 Glossary update interval 2 Unip/Bip channel unipolar/bipolar bit volts input voltage reference don’t care bits © National Instruments Corporation PCI E Series RLPM...

  • Page 152: Index

    4-29 to 4-31 function analog input circuitry acquiring one sample from channel 0, 4-10 block diagram, 2-8 AMUX-64T examples theory of operation, 2-8 to 2-11 sampling one channel, 4-27 scanning eight channels, 4-29 © National Instruments Corporation PCI E Series RLPM...
  • Page 153 Analog Output Register Group waveform generation examples AO Configuration Register, 3-16 to 3-17 using interrupts, 4-43 DAC FIFO Data Register, 3-18 using local buffer mode, 4-41 DAC0 Direct Data Register, 3-19 using polled writes, 4-38 PCI E Series RLPM © National Instruments Corporation...
  • Page 154 Chan<3..0>, 3-12 to 3-15 PCI-6024E and PCI-6025E map ChanType<2..0>, 3-11 (table), 5-10 to 5-11 D<15..0>, 3-8, 3-18, 3-19, 3-20 PCI-6052E map (table), 5-12 to 5-14 DACSel, 3-16 DitherEn, 3-9 to 3-10 DOTRIG0, 4-52 © National Instruments Corporation PCI E Series RLPM...
  • Page 155 (table), 3-13 to 3-14 start, 4-22 referenced single-ended channel with interrupts, 4-16 assignments (table), 3-14 single wire acquisition, 4-26 valid channel types (table), 3-11 ChanType<2..0> bit, 3-11 PCI E Series RLPM © National Instruments Corporation...
  • Page 156 2-11 to 2-18 4-58 to 4-59 ADC timing (figure), 2-12 programming MITE for different DMA block diagram, 2-8 transfers, 4-20 to 4-21 data acquisition sequence timing, structure (figure), 4-57 2-12 to 2-18 © National Instruments Corporation PCI E Series RLPM...
  • Page 157 GenTrig bit, 3-9 analog output, 2-22 GENTRIG0 signal, 4-52 configuration memory, 2-8 getvect() function, 4-14 overflow, 2-11 ghost channel theory of operation, 2-10 to 2-11 definition, 2-9 waveform generation, 2-23 to 2-24 PCI E Series RLPM © National Instruments Corporation...
  • Page 158 Link Chaining Mode for DMA transfer, 4-58 to 4-59 programming for different DMA transfers, 4-20 to 4-21 initializing PCI re-mapping PCI E Series board, 4-3 for IBM compatible systems, 4-2 MITE_DMAarm function, 4-17, 4-20 for Macintosh computers, 4-4 MITE_DMAdisarm function, 4-17, 4-20 Input<D..A>...
  • Page 159 4-25 theory of operation, 2-9 posttrigger acquisition, 2-18 to 2-19 pretrigger acquisition, 2-18 to 2-19 operation of PCI E Series boards. See theory of programmable gain instrumentation amplifier operation. (PGIA). See PGIA (programmable gain OUT signal, timing I/O circuitry, 2-25 instrumentation amplifier).
  • Page 160 PROMOUT bit, 3-6, 5-1 windowed registers pulse train generation example, 4-49 to 4-52 programming considerations, 4-5 pulsewidth measurement example, register map, 3-2 4-47 to 4-49 ReGlitch bit, 3-17 Pulse_Width_Measurement_ISR reglitch circuitry, 2-22 function, 4-48 © National Instruments Corporation PCI E Series RLPM...
  • Page 161 Index digital I/O examples, 4-7 re-mapping PCI E Series board, 4-3 to 4-4 RTSI bus interface circuitry general-purpose counter/timer examples block diagram, 2-26 gated event counting, 4-45 theory of operation, 2-25 to 2-26 initializing PCI IBM compatible systems, 4-2 RTSI trigger lines, programming...
  • Page 162 PCI-MIO-6052E, and analog triggering PCI-6031E, 2-2 programming considerations, PCI-MIO-16XE-50, 2-5 4-52 to 4-56 components of PCI E Series boards, 2-5 theory of operation, 2-19 to 2-20 data acquisition timing circuitry, posttrigger and pretrigger acquisition, 2-11 to 2-18 2-18 to 2-19...

This manual is also suitable for:

Pci-6023ePci-mio-16e-4Pci-mio-16e-1Pci-mio-16xe-50Pci-6024ePci-6025e ... Show all

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