National Instruments PCI-6251 User Manual page 245

Appendix B Timing Diagrams
Analog Output Timing Diagrams
The analog output timing can be broken into the following three sections:
Input Timing—The timing for external signals to enter the M Series device and be available
•
on the internal signal buses.
Internal Analog Output
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to and from internal signals.
Output Timing—The timing of exported signals going to the M Series device external
•
terminals.
Figure B-22 gives an overview of analog output timing.
STAR_TRIG,
RTSI, or
PFI
STAR_TRIG_i,
RTSI_i, or
PFI_i
The following signals are used in Figure B-22 and in the following sections:
Sample Clock—This signal multiplied by the digital to analog conversions. This signal is
•
routed to the DAC, and in every pulse, the DAC will perform a data conversion. This signal
can come directly from an external signal or can be the result of dividing down the Sample
Clock Timebase using the UI counter.
Sample Clock Timebase—This signal can be used to generate the Sample Clock. This
•
signal acts as the clock for the UI counter, and a Sample Clock can be generated every
N periods of the Sample Clock Timebase by programming the UI counter accordingly. This
signal can come from an internal source (such as the board oscillator) or an external source.
Sync Sample Clock Timebase—The Sync Sample Clock Timebase is a signal that is
•
generated internally and is related to the Sample Clock Timebase. How it is generated and
B-20 | ni.com
Timing—The timing specifications of the analog output unit itself,
Figure B-22. M Series Analog Output Timing
Internal
Sources
Sample
Clock
Timebase
Selected
Start
Trigger
Selected Pause
AO Timer
Sample Clock
Start Trigger
Pause Trigger
Other
Internal
Sources
PFI
RTSI