National Instruments PCI-6251 User Manual page 252

Figure B-34. Pause Trigger Output Routing Delay Timing Diagram
Selected Pause Trigger
Table B-20. Pause Trigger Output Routing Delay Timing
Time From
t Selected Pause
13
Trigger
Sample Clock—The rising edge of the Sample Clock is output synchronous to the Sample
•
Clock Timebase. It can be calculated by adding the Sample Clock Timebase insertion to the
delay in Table B-21. The exported Sample Clock signal is active low, each falling edge
representing a conversion.
Internal Logic
Sample Clock Timebase
Sample Clock Timebase
Time
t AO Sample Clock
14
AO Sample Clock
RTSI Terminal
To
RTSI
Figure B-35. Sample Clock Path
D
Figure B-36. Sample Clock Delay Timing Diagram
RTSI/PFI Terminal
Table B-21. Sample Clock Delay Timing
From
PFI
RTSI
t
13
t
13
Min (ns)
6.7
To Internal Logic
Q
t
14
To Min (ns)
9.7
8.8
M Series User Manual
Max (ns)
7.1 16.3
Routing Logic
Max (ns)
10.7 31.1
9.1 21.3
© National Instruments | B-27
17.0
RTSI, PFI
34.3
21.7