Modes Of Operation; State-Per-Transfer Mode; State-Per-Clock Mode; Timing Mode - HP E2416B User Manual

Modes of Operation

The HP E2416B Analysis Probe can be used in three different analysis
modes: State-per-transfer, State-per-clock, and Timing.

State-per-transfer mode

In State-per-transfer mode, the analysis probe demultiplexes the 16-bit
address/data bus into 16-bit address and 16-bit data. The address/data bus
goes through two levels of latches. The first level is flowthrough latches,
which provides information to the logic analyzer about the data bus. The
second level latches on the falling edge of ALE to capture address
information. The analysis probe generates a master clock to clock
information to the logic analyzer when Read or Write is deasserted.
State-per-transfer is the default mode set up by the configuration files.
Inverse assembly is available in State-per-transfer mode.

State-per-clock mode

In State-per-clock mode, a state is captured on every rising edge of the
microprocessor clock, regardless of the validity of the bus cycle. To use
State-per-clock mode, change the clock in the Format menu from J rising
edge to K rising edge. K clock is a duplicate of the microprocessor CLKOUT.
Inverse assembly is not supported in State-per-clock mode.

Timing mode

In Timing mode, the latches on the analysis probe act like flow-through
buffers. The signals from the microprocessor go directly from the target
system to the logic analyzer, with a 1-ns channel-to-channel skew.
To configure the logic analyzer for timing analysis:
Select the Configuration menu of the logic analyzer.
1
Select the Type field for the analyzer and select Timing.
2
Timing data is displayed in the Waveform menu of the logic analyzer.
HP E2416B 80196 Analysis Probe 3-3