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PRINCIPLES OF OPERATION ·
1
iv
I
This
section
contains
functional-level
and
system-level
descriptions
of
the
HP
30010A
Intelligent
Network Processor
(INP).
The functional description
lists
the
major
functional
areas
and
briefly
describes
each
of
them.
An example of a
typical
functional-level
operation
follows,
which
serves
to
summarize
the
functional des er ip tion.
Then, an overview of the
system-level
operation
briefly
discusses
INP
operations
in
relation to the HP 3000 Series II or Series III Computer System.
4-1.
FUNCTIONA~
DESCRIPTION
The HP 30010A Intelligent Network Processor includes the
follow-
ing major functional areas:
•
INP Microprocessor
•
Read-Only Memory (ROM)
•
Random Access Memory (RAM)
•
Direct Memory Access (Dtl.A)
•
SDLC and BISYNC Datacomm
•
Communication Line Interfaces
A block diagram of INP organization of the major functional areas
is shown in figure 4-1.
The solid interconnecting lines
in
the
block
diagram
represent
data
paths
while
the
broken
lines
indicate service request paths.
4 ·2. INP Microprocessor
The Complementary-Metal-Oxide-Semiconductor
I
Silicon-on-Sapphire
(CMOS/SOS) Microprocessor is the heart of the INP.
It is a high-
performance, low-power-consumption microprocessor primarily
used
in
controller applications.
It offers a one-microsecond typical
instruction cycle time to execute any of the fixed-width,
16-bit
instructions.
These
instructions
can
process
one-,
four-i
eight-, or sixteen-bit fields.
The fast instruction
cycle
time
4-1