Peak/Pit Detection - HP 8560E Service Manual

5. Pins 4 through 10 (ADC7-ADC1) and pin 21 (ADC0) of U35 should
all be low (logic 0), corresponding to an ADC digital count of zero for
the analog input of 0 volts or less.

Peak/Pit Detection

Refer to function block J of the A16 fast ADC assembly schematic
diagram in the HP 8560 E-Series Component Level Information.
Peak detection or pit (negative peak) detection can be enabled
whenever the sample rate is less than 12 MHz (sweep times greater
than 50 µs). Peak detection uses the maximum value of all the samples
taken within each bucket (between adjacent display points). Pit
detection uses the minimum value of all the samples taken within each
bucket. And sample detection uses the last sample of all the samples
taken within each bucket.
The different detection modes are implemented by selectively clocking
latch U30, depending on the state of LP/Q which is generated in PAL
U1 (block A). When LP/Q is low, U30 is clocked by WCLK. When LP/Q
is high, U30 is not clocked. LP/Q is a function of the 12M_SEL, SCLK-1,
LSAMPLE, LPEAK, P_LO, and P_HI signals. See
page 392.
If the sample rate is 12 MHz, 12M_SEL is high, which forces LP/Q low
so that every sample is clocked into latch U30 and latched into RAM
U32 (block K). If the sample rate is less than 12 MHz and the detection
mode is peak or pit, the SCLK-1, LPEAK, P_LO, and P_HI signals
control the LP/Q signal. In these detection modes, latch U30 stores the
peak or pit value of the samples taken for each bucket. The 8-bit digital
magnitude comparator, U31, compares the input byte (P) with the
output byte (Q) from latch U30. When P is greater than Q, P_LO is low
(0) and P_HI is high (1). When P is less than Q, P_LO is high (1) and
P_HI is low (0). When P is equal to Q, P_LO and P_HI are both low (0).
See Table 7-12 on page
Chapter 7
A16 Assembly Fast ADC Circuits (8560E with Option 007)
392.
ADC/Interface Section
Table 7-12 on
391