Sch04_Main Power - Denon DRA-100 Service Manual

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1
2
3
A
CN1001
C1002
C1003
3300/35(18*40)-RFA
3300/35(18*40)-RFA
+32V
B
CN1001
3P_WIRE
+32V
GND
-32V
-32V
C1005
C1006
TO CN221
3300/35(18*40)-RFA
3300/35(18*40)-RFA
C
D
E
220/50(10*16)-RFY
CN1002
C1009
+12V
100N-K
C1010
GND
220/50(10*16)-RFY
+9V
C1011
C1012
GND
220/50(10*16)-RFY
100N-K
F
-9V
GND
+18V
C1014
C1013
GND
100/25(6.3*11)-RFO
100N-K
GND
C1015
C1017
+5V
-
470/16(10*12.5)-RFO
+5V
R1063
10
C1016
P/D
100N-K
R1062
10
CTR_PWR1
Q1008
R1086
10
CTR_PWR2
PBSS5140U
CN1002
G
R1032
14P_WIRE
10K
TO CN222
Q1009
RT1N141C
BD1012
0
H
BD1015
0
J
BD1016
K
0
BD1017
0
L
M
GND LINE
POWER+ LINE
POWER- LINE
ANALOG AUDIO R
1
2
3
4
5
6
DRA-100 MAIN - POWER (4/9)
L1001
4.7UH
IC1001
TPS562200
1
GND
VBST
6
BD1001
R1016
BKP_HS101-2125
2
SW
EN
5
100
3
VIN
VFB
4
BD1002
BKP_HS101-2125
CTR_PWR2
C1054
47/50(6.3*11)-RFO
IC1005
NGD
NJM2387ADL3
6
Vin
GND
Vout
1
5
2
4
-32V
Vout
R1088
Control
Vadj
3
100
C1051
47/50(6.3*11)-RFO
Q1001
BC807
Q1003
+9VA
BC817
R1003
-9VA
10K
R1005
47K
SMPS_+12V
Q1002
Q1018
RT1N141C
PBSS5140U
R1089
10K
R1027
3K3
SMPS_+9V
C1055
10000N-K
Q1004
SMPS_-9V
-9VA
RT1N141C
18V_OLED
P/D
CTR_CSR
CTR_PWR1
5V_ANA
R1060
100
3V3_STBY
AP7361-ADJ
IC1008
5
4
OUT
IN
EN
GND
ADJ
R1030
1
2
3
1K
CPU POWER
3V3_D
AP7361-ADJ
IC1009
5
4
OUT
IN
EN
GND
ADJ
R1034
1
2
3
100
CTR_3V3_DSP
Q1010
RAQ045P01
1V2_D
AP7361-ADJ
4
5
6
IC1010
5
4
3
2
1
OUT
IN
EN
GND
ADJ
1
2
3
R1061
R1037
100
100
Q1011
CTR_FPGA
RT1N141C
CTR_1V2_DSP
2V5_FPGA
AP7361-ADJ
IC1011
5
4
OUT
IN
EN
GND
ADJ
1
2
3
R1040
100
DSP/DIR/FPGA POWER BLOCK
CTR_FPGA
ANALOG AUDIO L
DIGITAL AUDIO
SUBWOOFER
4
5
6
7
8
9
10
BD1003
BKP_HS101-2125
BD1004
BKP_HS101-2125
AP7361-ADJ
IC1002
5
4
OUT
IN
EN
GND
ADJ
1
2
3
R1017
1K
BD1005
BKP_HS101-2125
AP7361-ADJ
R1023
IC1003
1
5
4
OUT
IN
EN
GND
ADJ
R1024
1
2
3
R1021
1
1K
BD1006
BKP_HS101-2125
IC1004
LP5900SD
1
Vout
Vin
6
7
2
N/C
N/C
5
GND
3
GND
Ven
4
C1042
-
Q1005
PBSS5140U
R1007
10K
IC1006
NJM78L05UA
1
3
OUTPUT
INPUT
2 GND
Q1006
RT1N141C
IC1007
NJM79L05UA
COMMON
1
3 OUTPUT
2 INPUT
BD1018
0
BD1019
0
BD1020
0
BD1021
0
7
8
9
10
49
11
12
13
A0
+32V
-32V
D1001
TO SPKOUT SHEET
R1066
GND
Q1012
LBAS16HT1G
47K
RT1N141C
NGD
SMPS_+9V
TO 0A
5V25_CSR
+9VA
Q1013
A1
R1010
5V25
RT1N141C
100K
3V3_CSR
SMPS_-9V
BD1008
BK_HS601
S3V3_CSR
Q1015
R1071
RT1N141C
100K
1V8_CSR
SMPS_+12V
TO CSRA SHEET
C1V8_CSR
BD1009
BK_HS601
R1V8_CSR
BD1010
BK_HS601
Q1016
R1074
S1V8_CSR
RT1N141C
100K
R3V3_CSR
18V_OLED
A3V3_CSR
TO 1A
BD1011
BD102
+5VA
-5VA
A2
GND
+9VA
TO PREOUT SHEET
-9VA
TO 2A
3V3_STBY
BD1023
0
C1075 10000N-K
BD1024
0
AP7361-ADJ
IC1013
A3
CTR_1V2_CY920
CTR_1V8_CY920
R1052
100
CTR_2V5_CY920
CTR_3V3_CY920
CTR_CSR
P/D
CTR_PWR1
BD1025
CTR_PWR2
0
CTR_3V3_DSP
TO 3A
CTR_1V2_DSP
TO CPU/CY920 SHEET
CTR_FPGA
A4
18V_OLED
C1090
10000N-K
GND
R1078
-
TO 4A
BD1026
0
AP7361-ADJ
3V3_STBY
IC1015
GND
BD1014
A5
0
5V_USB
3V3_CY920
2V5_CY920
R1058
100
1V8_CY920
TO 5A
1V2_CY920
BD1022
0
A6
5V_ADC
3V3_D
GND
TO 6A
3V3_DIR
3V3_DSP
TO DSP/DIR/FPGA SHEET
1V2_DSP
A7
3V3_FPGA
1V2_FPGA
TO 7A
2V5_FPGA
SCHEMATIC DIAGRAMS (04/10)

SCH04_MAIN POWER

11
12
13
14
15
16
A
A8
R1068
10K
3V3_STBY
D1002
GND
LBAS16HT1G
A_DC_PROT1
TO CPU/CY920 SHEET
R1069
A_DC_PROT2
10K
TO 8A
D1003
LBAS16HT1G
B
Q1014
RT1N141C
R1070
10K
R1073
10K
D1004
LBAS16HT1G
C
R1076
10K
D1005
LBAS16HT1G
D
CY920 POWER BLOCK
L1002
3.3UH
3V3_CY920
IC1012
TPS562200
1
GND
VBST
6
E
2
SW
EN
5
3
VIN
VFB
4
C1072
22000N-M
2V5_CY920
5
4
F
OUT
IN
EN
GND
ADJ
1
2
3
L1003
2.2UH
1V8_CY920
IC1014
TPS562200
1
6
GND
VBST
G
2
SW
EN
5
3
VIN
VFB
4
C1091
22000N-M
1V2_CY920
H
5
4
OUT
IN
EN
GND
ADJ
1
2
3
J
K
L
M
14
15
16

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