Denon DRA-100 Service Manual page 69

CSRA6601 (IC1701)
2 Packaging Information
2.1 CSRA6601 Pinout Diagram
MCK0_OUT 1
MCK0_OUT_BAR 2
CKO0P1V8 3
CKO0GND 4
PWMCK0_OUT 5
CKO0P3V3 6
P1V8 7
GND 8
C1P1V8 9
CH1_REF0 10
C1P3V3 11
C1GND 12
CH1_REF1 13
CH1_REF2 14
CH1_FB0 15
CH1_FB1 16
C01P1V8 17
C01GND 18
C01P3V3 19
CH0_FB1 20
CH0_FB0 21
CH0_REF2 22
CH0_REF1 23
C0GND 24
C0P3V3 25
CH0_REF0 26
C0P1V8 27
P1V8 28
GND 29
P3V3 30
CH3_PWM2 31
CH3_PWM1 32
CH3_PWM0 33
CH2_PWM2 34
CH2_PWM1 35
CH2_PWM0 36
GND 37
P3V3 38
CH1_PWM2 39
CH1_PWM1 40
CH1_PWM0 41
CH0_PWM2 42
CH0_PWM1 43
CH0_PWM0 44
Figure 2.1: CSRA6601 Pinout Diagram
2.2 CSRA6601 Device Terminal Functions
Pin Name
1 MCK0_OUT
Production Information
2 MCK0_OUT_BAR
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
3 CKO0P1V8
4 CKO0GND
5 PWMCK0_OUT
6 CKO0P3V3
7 P1V8
8 GND
9 C1P1V8
10 CH1_REF0
11 C1P3V3
12 C1GND
13 CH1_REF1
14 CH1_REF2
15 CH1_FB0
16 CH1_FB1
17 C01P1V8
18 C01GND
19 C01P3V3
20 CH0_FB1
21 CH0_FB0
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
Function Description
Output, tristate 108 MHz Master clock output channels 0,
1, 2, 3
Output, tristate 108 MHz Master clock bar output
channels 0, 1, 2, 3
- 1.8 V core supply (quiet)
- Ground
Output, tristate PWM triangle generator output channels
0, 1, 2, 3
- 3.3 V I/O supply (quiet)
- 1.8 V core supply (quiet)
- Ground
- 1.8 V core supply (quiet)
Output, tristate Channel 1 reference 0 output
- 3.3 V I/O supply (quiet)
- Ground
Output, tristate Channel 1 reference 1 output
Output, tristate Channel 1 reference 2 output
Bidirectional, pull-up Channel 1 low resolution feedback input
or channel 0/1 I²S output word clock
Bidirectional, pull-up Channel 1 high resolution feedback input
or channel 0/1 I²S output data
- 1.8 V core supply (quiet)
- Ground
- 3.3 V I/O supply (quiet)
Bidirectional, pull-up Channel 0 high resolution feedback input
or channel 0/1 I²S output bit clock
Bidirectional, pull-up Channel 0 low resolution feedback input
69
132 MCK1_OUT
131 MCK1_OUT_BAR
130 CKO1P1V8
129 CKO1GND
128 PWMCK1_OUT
127 CKO1P3V3
126 P1V8
125 GND
124 C6P1V8
123 CH6_REF0
122 C6P3V3
121 C6GND
120 CH6_REF1
119 CH6_REF2
118 CH6_FB0
117 CH6_FB1
116 C67P3V3
115 C67GND
114 C67P1V8
113 CH7_FB1
112 CH7_FB0
111 CH7_REF2
110 CH7_REF1
109 C7GND
108 C7P3V3
107 CH7_REF0
106 C7P1V8
105 P1V8
104 GND
103 P3V3
102 CH4_PWM2
101 CH4_PWM1
100 CH4_PWM0
99 CH5_PWM2
98 CH5_PWM1
97 CH5_PWM0
96 GND
95 P3V3
94 CH6_PWM2
93 CH6_PWM1
92 CH6_PWM0
91 CH7_PWM2
90 CH7_PWM1
89 CH7_PWM0
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