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6 Pin Configuration and Functions
TPS562200 (IC1001, IC1014, IC1012)
TPS562200, TPS563200
SLVSCB0B – JANUARY 2014 – REVISED AUGUST 2014
8 Detailed Description
PIN
NAME
NUMBER
8.1 Overview
GND
The TPS562200 and TPS563200 are 2-A and 3-A synchronous step-down converters. The proprietary D-
SW
CAP2™mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer
ceramic capacitors without complex external compensation circuits. The fast transient response of D-CAP2™
VIN
mode control can reduce the output capacitance required to meet a specific level of performance.
VFB
EN
8.2 Functional Block Diagrams
VBST
Block Diagram
EN
5
4
VFB
Copyright © 2014, Texas Instruments Incorporated
10
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TPS562200, TPS563200
GND
1
SW
2
VIN
3
Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit.
1
Connect sensitive VFB to this GND at a single point.
2
Switch node connection between high-side NFET and low-side NFET.
3
Input voltage supply pin. The drain terminal of high-side power NFET.
4
Converter feedback input. Connect to output voltage with feedback resistor divider.
5
Enable input control. Active high and must be pulled up to enable the device.
6
Supply input for the high-side NFET gate drive circuit. Connect a 0.1µF capacitor between VBST and SW pins.
+
V
Hiccup
UVP
UVP
+
OVP
V
OVP
PWM
Voltage
Ref
+
Reference
+
SS
Soft Start
Ton
One-Shot
TSD
OCL
threshold
OCL
+
Product Folder Links:
+
ZC
Figure 19. Functional Block Diagram: TPS562200 and TPS563200
Product Folder Links:
SLVSCB0B – JANUARY 2014 – REVISED AUGUST 2014
DDC Package
Top View
VBST
6
EN
5
VFB
4
Pin Functions
DESCRIPTION
Control Logic
Regulator
UVLO
XCON
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TPS562200 TPS563200
Copyright © 2014, Texas Instruments Incorporated
TPS562200 TPS563200
80
TPS562200, TPS563200
www.ti.com
3
VIN
VREG5
VBST
6
HS
2
SW
VREG5
LS
1
GND
3
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