Denon DRA-100 Service Manual page 70

Pin Name
22 CH0_REF2
23 CH0_REF1
24 C0GND
25 C0P3V3
26 CH0_REF0
27 C0P1V8
28 P1V8
29 GND
30 P3V3
31 CH3_PWM2
32 CH3_PWM1
33 CH3_PWM0
34 CH2_PWM2
35 CH2_PWM1
36 CH2_PWM0
37 GND
38 P3V3
39 CH1_PWM2
40 CH1_PWM1
41 CH1_PWM0
42 CH0_PWM2
43 CH0_PWM1
Pin Name Function
Production Information
44 CH0_PWM0 Output
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
45 P3V3 -
46 GND -
47 P1V8 -
48 CH_0_1_AUDIO_SCK Input, pull-down
49 CH_0_1_AUDIO_SD Input, pull-down
50 CH_0_1_AUDIO_WS Input, pull-down
51 CH_2_3_AUDIO_SCK Input, pull-down
52 CH_2_3_AUDIO_SD Input, pull-down
53 CH_2_3_AUDIO_WS Input, pull-down
54 PWM_MODE Input, pull-down
55 GPIO_0 Bidirectional, pull-down
56 GPIO_1 Bidirectional, pull-down
57 P3V3 -
58 GND -
59 P1V8 -
60 GPIO_2 Bidirectional, pull-down
61 INTERRUPT Output
62 BRIDGE_ON Input, pull-down
63 RESET_BAR Input, pull-up
64 MCK_SEL Input, pull-down
65 GPIO_3 Bidirectional, pull-down
66 GND -
67 P3V3 -
68 GPIO_4 Bidirectional, pull-down
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
Function Description
Output, tristate Channel 0 reference 2 output
Output, tristate Channel 0 reference 1 output
- Ground
- 3.3 V I/O supply (quiet)
Output, tristate Channel 0 reference 0 output
- 1.8 V core supply (quiet)
- 1.8 V core supply
- Ground
- 3.3 V I/O supply
- Output Channel 3 high side drive
- Bidirectional, pull-down Channel 3 high
side drive or channel 2/3 PWM sense
control
- Output Channel 3 low side drive
Output Channel 2 high side drive
Bidirectional, pull-down Channel 2 high side drive or channel 2/3
PWM sense control
Output Channel 2 low side drive
- Ground
- 3.3 V I/O supply
Output Channel 1 high side drive
Bidirectional, pull-down Channel 1 high side drive or channel 0/1
PWM sense control
Output Channel 1 low side drive
Output Channel 0 high side drive
Bidirectional, pull-down Channel 0 high side drive or channel 0/1
PWM sense control
Description
Channel 0 low side drive
3.3 V I/O supply
Ground
1.8 V core supply
Channels 0, 1 audio input bit clock
Channels 0, 1 audio input data
Channels 0, 1 audio input word clock
Channels 2, 3 audio input bit clock
Channels 2, 3 audio input data
Channels 2, 3 audio input word clock
2 wire vs 3 wire PWM mode control
GPIO
GPIO
3.3 V I/O supply
Ground
1.8 V core supply
GPIO
System interrupt
Bridge on/off control
Global reset
Master clock circuit select
GPIO
Ground
3.3 V I/O supply
GPIO
70
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CS-225959-DSP6
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Page 17 of 181
CS-225959-DSP6
www.csr.com