CY8C20234 (IC301)
16-Pin Part Pinout
PSoC
®
Programmable System-on-Chip™
Features
®
Low power CapSense
block
■
Configurable capacitive sensing elements
❐
Supports combination of CapSense buttons, sliders,
❐
touchpads, and proximity sensors
Powerful Harvard-architecture processor
■
M8C processor speeds running up to 12 MHz
❐
Low power at high speed
❐
Operating voltage: 2.4 V to 5.25 V
❐
Industrial temperature range: –40 °C to +85 °C
❐
Flexible on-chip memory
■
Block Diagram
8 KB flash program storage 50,000 erase/write cycles
❐
Table 5. Pin Definitions – CY8C20234 16-Pin (QFN no e-pad)
512-Bytes SRAM data storage
❐
Partial flash updates
❐
Pin No.
Flexible protection modes
❐
Interrupt controller
❐
1
In-system serial programming (ISSP)
❐
2
Complete development tools
■
3
Free development tool (PSoC Designer™)
❐
Full-featured, in-circuit emulator, and programmer
4
❐
Full-speed emulation
❐
5
Complex breakpoint structure
❐
128 KB trace memory
6
❐
Precision, programmable clocking
7
■
Internal ±5.0% 6- / 12-MHz main oscillator
8
❐
Internal low speed oscillator at 32 kHz for watchdog and sleep
❐
9
Programmable pin configurations
■
10
Pull-up, high Z, open-drain, and CMOS drive modes on all
❐
11
GPIOs
Up to 28 analog inputs on all GPIOs
❐
12
Configurable inputs on all GPIOs
❐
13
20-mA sink current on all GPIOs
❐
14
Selectable, regulated digital I/O on port 1
❐
• 3.0 V, 20 mA total port 1 source current
15
• 5 mA strong drive mode on port 1 versatile analog mux
16
Common internal analog bus
❐
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
Simultaneous connection of I/O combinations
❐
Comparator noise immunity
❐
Pin Discription
Low-dropout voltage regulator for the analog array
❐
Pin No.
1
2
3
Note
6. These are the ISSP pins, that are not High Z at POR (Power-on-Reset). See the
4
5
Document Number: 001-05356 Rev. *Q
6
Cypress Semiconductor Corporation
7
Document Number: 001-05356 Rev. *Q
8
9
10
11
12
13
14
15
16
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive
CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
®
PSoC
Programmable System-on-Chip™
Figure 5. CY8C20234 16-Pin PSoC Device
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
Additional system resources
■
Configurable communication speeds
❐
2
• I
C: selectable to 50 kHz, 100 kHz, or 400 kHz
• SPI: configurable between 46.9 kHz and 3 MHz
2
I
C slave
❐
SPI master and SPI slave
❐
Watchdog and sleep timers
❐
Internal voltage reference
❐
Integrated supervisory circuit
❐
Logic Block Diagram
Type
Name
Digital
Analog
I/O
I
P2[5]
I/O
I
P2[1]
I
I
P1[7]
OH
I
I
P1[5]
OH
I
I
P1[3]
OH
I
I
P1[1]
OH
Power
V
SS
I
I
P1[0]
OH
I
I
P1[2]
OH
I
I
P1[4]
OH
Input
XRES
I/O
I
P0[4]
Power
V
DD
I/O
I
P0[7]
I/O
I
P0[3]
I/O
I
P0[1]
Type
Name
Digital
Analog
I/O
I
P2[5]
I/O
I
P2[1]
I
I
P1[7]
OH
I
I
P1[5]
OH
I
I
P1[3]
OH
I
I
P1[1]
OH
•
198 Champion Court
•
Power
V
SS
I
I
P1[0]
OH
I
I
P1[2]
OH
I
I
P1[4]
OH
Input
XRES
I/O
I
P0[4]
Power
V
DD
I/O
I
P0[7]
I/O
I
P0[3]
I/O
I
P0[1]
CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
AI, P2[5]
1
P0[4], AI
12
2
AI, P2[1]
XRES
QFN
11
(Top View)
3
10
P1[4], AI, EXTCLK
4
9
P1[2], AI
Port 3
Port 2
Port 1
Port 0
Config LDO
PSoC
CORE
System Bus
2
I
C SCL, SPI SS
2
Global Analog Interconnect
I
C SDA, SPI MISO
SRAM
SROM
Flash 8K
512 Bytes
SPI CLK
CPU Core
Sleep and
[6]
2
Interrupt
(M8C)
CLK
, I
C SCL, SPI MOSI
Watchdog
Controller
Ground connection
6/12 MHz Internal Main Oscillator
[6]
2
DATA
, I
C SDA
Optional external clock input (EXTCLK)
Analog
Ref.
ANALOG
CapSense
Active high external reset with internal pull-down
SYSTEM
Block
Supply voltage
Integrating Input
POR and LVD
I2C Slave/SPI
Analog
Master-Slave
Mux
System Resets
SYSTEM RESOURCES
2
I
C SCL, SPI SS
PSoC Technical Reference Manual
2
I
C SDA, SPI MISO
SPI CLK
[6]
2
CLK
, I
C SCL, SPI MOSI
,
San Jose
CA 95134-1709
•
Ground connection
Revised June 15, 2012
[6]
2
DATA
, I
C SDA
Optional external clock input (EXTCLK)
Active high external reset with internal pull-down
Supply voltage
Integrating Input
79
Description
Description
for details.
408-943-2600
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