Denon DRA-100 Service Manual page 68

Pin Name Function
25 C1S1O Stage 1 output
26 C1S2O Stage 2 output
27 C1S2I Stage 2 input
28 C1S2PCK Stage 2 PWM clock input
29 C1P5 5 V
30 C1N5 -5 V
31 C1N5D -5 V dig
32 C1S1MCKB Stage 1 master clock bar input
33 C1S2MCKB Stage 2 master clock bar input
34 C1P5D 5 V digital
35 C1GND Ground
36 C0GND Ground
37 C0P5D 5 V digital
38 C0S2MCK Stage 2 master clock input
39 C0S1MCK Stage 1 master clock input
40 C0N5D -5 V digital
Bottom Tab - Connect to Pins 1 and 30
Table 2.2: CSRA6600 Device Terminal Functions
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
68
Channel
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0,1
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