Hdmi; Figure 9-8. Hdmi Connection Example - Nvidia Jetson Orin NX Design Manual

9.2

HDMI

A standard DP 1.4 or HDMI v2.1 interface is supported. See Figure 9-8 for more details.
Figure 9-8. HDMI Connection Example
Jetson
SoC – DP/HDMI
DP1_HPD
GP74_HPD0_N
DP1_AUX_N
SF_DPAUX01_P
DP1_AUX_P
SF_DPAUX01_N
HDMI_CEC
GP05_HDMI_CEC
DP1_TXD3_N
HS_DISP0_HDMI_CK_DP3_P
DP1_TXD3_P
HS_DISP0_HDMI_CK_DP3_N
DP1_TXD2_N
HS_DISP0_HDMI_D0_DP2_P
DP1_TXD2_P
HS_DISP0_HDMI_D0_DP2_N
DP1_TXD1_N
HS_DISP0_HDMI_D1_DP1_P
DP1_TXD1_P
HS_DISP0_HDMI_D1_DP1_N
DP1_TXD0_N
HS_DISP0_HDMI_D2_DP0_P
DP1_TXD0_P
HS_DISP0_HDMI_D2_DP0_N
Load Switch
VDD_3V3_SYS
IN OUT
MOD_SLEEP*
EN
100kΩ
Notes:
1. Level shifters required on DDC/HPD. NVIDIA Orin pads are not 5V tolerant and cannot
directly meet HDMI VIL/VIH requirements. HPD level shifter can be non-inverting or
inverting. The HPD level shifter in the reference design is inverting. The reference design
uses a BJT level shifter, and a resistor divider is needed. See the reference design if a
similar approach will be used.
2. If EMI/ESD devices are necessary, they must be tuned to minimize the impact to signal
quality, which must meet the timing and electrical requirements of the HDMI specification
for the modes to be supported. See requirements and recommendations in the related
sections of the "HDMI Interface Signal Routing Requirements" table (Table 9-5).
3. The DP1_TXx pads are native DP pads and require series AC capacitors (ACCAP) and pull-
downs (RPD) to be HDMI compliant. The 499 Ω, 1% pull-downs must be disabled when Jetson
Orin NX is off or in sleep mode to meet the HDMI VOFF requirement. The enable to the FET,
enables the pull-downs when the HDMI interface is to be used. Chokes between pull-downs
and FET are optional improvements for HDMI 2.0 operation.
4. See the RS section in Table 9-5 for details.
5. See reference design for CEC level shifting and blocking circuit.
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Load Switch
VDD_5V_SYS
IN OUT
EN
VDD_1V8 VDD_3V3_HDMI
0.1uF
96
Level Shifter
98
3.3V 5V
100
Shifter Circuit
94
0.1uF
81
0.1uF
83
0.1uF
75
0.1uF
77
0.1uF
69
0.1uF
71
0.1uF
63
0.1uF
65
499Ω,1%
VDD_3V3_HDMI
FET
G D
10kΩ
S
VDD_5V0_HDMI_CON
Level Shifter
1.8V 5V
CEC Level
(see note)
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
See
Note 4
TPD4E 02B04 DQO R
Display
HDMI
Type A
HP_DET
19
+5V
18
DDC/CEC_GND
17
SDA
16
SCL
15
RESERVED
14
CEC
13
CK–
12
CK_SHIELD
11
CK+
10
D0–
9
D0_SHIELD
8
D0+
7
D1–
6
D1_SHIELD
5
D1+
4
D2–
3
D2_SHIELD
2
D2+
1
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