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12.2.1
SPI Design Guidelines
The following guidelines meet the SPI design guidelines.
Figure 12-4.
SPI Topologies
Point-Point Topology
Jetson
SPI
SoC
Device
Main trunk
Table 12-5.
SPI Interface Signal Routing Requirements
Parameter
Max frequency
Configuration / device organization
Max loading (total of all loads)
Reference plane
Breakout region impedance
Max PCB breakout delay
Trace impedance
Via proximity (signal to reference)
Trace spacing: Microstrip / Stripline
Max trace length/delay (PCB main trunk) For MOSI, MISO, SCK and CS
Point-point
2x-load star/daisy
Max trace length/delay (Branch-A) for MOSI, MISO, SCK and CS
2x-load star/daisy
Max trace length/delay skew from MOSI, MISO and CS to SCK
Note: Up to four signal vias can share a single GND return via
Table 12-6.
SPI Signal Connections
Module Pin Names (Function)
SPI[1:0]_CLK
SPI[1:0]_MOSI
SPI[1:0]_MISO
SPI[1:0]_CS[1:0]*
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
2x-Load Star Topology
Jetson
Branch-A
SoC
Main trunk
Branch-B
Type
Termination
Description
I/O
SPI Clock.: Connect to peripheral CLK pins
I/O
SPI Data Output: Connect to target peripheral MOSI pins
I/O
SPI Data Input: Connect to target peripheral MISO pins
I/O
SPI Chip Selects.: Connect one CSx* pin per SPI interface to
each target peripheral CS pin on the interface
Miscellaneous Interfaces
2x-Load Daisy Topology
SPI
Device
#1
Jetson
SPI
SoC
Device
Main trunk
#2
Requirement
Units
65
MHz
4
load
15
pF
GND
Minimum width
and spacing
75
ps
50 – 60
Ω
< 3.8 (24)
mm (ps)
4x / 3x
dielectric
195 (1228)
mm (ps)
120 (756)
75 (472)
mm (ps)
16 (100)
mm (ps)
DG-10931-001_v0.1 | 65
SPI
Device
Branch-A
#1
SPI
Device
Branch-B
#2
Notes
±15%
See Note
At any point
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