Figure 2-1. Jetson Orin Nx Block Diagram; Table 2-2. Jetson Orin Nx Connector 260-Pin So-Dimm Pinout Matrix - Nvidia Jetson Orin NX Design Manual

Figure 2-1. Jetson Orin NX Block Diagram
VDD_IN
(5V-20V)
PMIC_BBAT
GBE_MDI
I2C 1x–1.8V
I2C 3x–3.3V
AUDIO MCLK
I2S 2x
DIGITAL MIC
SPI 2x
UART 3x
Table 2-2. Jetson Orin NX Connector 260-Pin SO-DIMM Pinout Matrix
Module Signal Name Jetson Orin NX
GND
CSI1_D0_N
CSI1_D0_P
GND
CSI1_CLK_N
CSI1_CLK_P
GND
CSI1_D1_N
CSI1_D1_P
GND
CSI3_D0_N
CSI3_D0_P
GND
CSI3_CLK_N
CSI3_CLK_P
GND
CSI3_D1_N
CSI3_D1_P
GND
DP0_TXD0_N USBSS1_RX_N
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Jetson Orin NX
LPDDR5
Power Seq.
Gigabit
CPU/GPU & Core Regs
Ethernet
Voltage Monitors
QSPI N OR
Orin
Pin #
Function
GND 1
CSI1_D0_N 3
CSI1_D0_P 5
GND 7
CSI1_CLK_N 9
CSI1_CLK_P 11
GND 13
CSI1_D1_N 15
CSI1_D1_P 17
GND 19
CSI3_D0_N 21
CSI3_D0_P 23
GND 25
CSI3_CLK_N 27
CSI3_CLK_P 29
GND 31
CSI3_D1_N 33
CSI3_D1_P 35
GND 37
39
Power
Subsystem
PCIe x1 + x2 + x4
[E]DP/HDMI 1x
DP_AUX/DDC
CSI: 2 x4 or 4 x2
CAM MCLK 2x
General Purpose
Pin # Module Signal Name
2 GND
4 CSI0_D0_N
6 CSI0_D0_P
8 GND
10 CSI0_CLK_N
12 CSI0_CLK_P
14 GND
16 CSI0_D1_N
18 CSI0_D1_P
20 GND
22 CSI2_D0_N
24 CSI2_D0_P
26 GND
28 CSI2_CLK_N
30 CSI2_CLK_P
32 GND
34 CSI2_D1_N
36 CSI2_D1_P
38 GND
40 CSI4_D2_N
Jetson Orin NX
USB 2.0 3x
USB 3.2 3x
NVMe for
HPD, CEC
Clocks 2x
PWM 3x
CAN 1x
Jetson Orin NX
Function
GND
CSI0_D0_N
CSI0_D0_P
GND
CSI0_CLK_N
CSI0_CLK_P
GND
CSI0_D1_N
CSI0_D1_P
GND
CSI2_D0_N
CSI2_D0_P
GND
CSI2_CLK_N
CSI2_CLK_P
GND
CSI2_D1_N
CSI2_D1_P
GND
PCIE2_RX0_N
DG-10931-001_v0.1 | 4
Storage