Figure 7-11. Zig-Zag Routing Example - Nvidia Jetson Orin NX Design Manual

Parameter
Max PCB via delay from the
Device/Connector
PCB within pair (intra-pair) skew
Within pair (intra-pair) matching between
subsequent discontinuities
Differential pair uncoupled delay
Via
Via placement
Max # of Vias
Max Via stub length
Value Min/Max
Voiding
Serpentine (See USB 3.2 Guidelines)
Serpentine
Min bend angle
Dimension
Min A Spacing
Min B, C Length
Min Jog Width
Miscellaneous
GND fill rule
Connector
Voiding
Keep critical PCIe traces such as PEX_TX/RX, etc. away from other signal traces or unrelated power traces and areas or power supply
components
Note:
1. This does not consider the loss of the end device or any additional connectors. These need to be accounted for and will reduce
the loss budget which will affect the max length or delay possible.
2. The max length and delay numbers are examples. These should be updated based on the actual PCB material loss and the loss
for the end device and any additional connections.
Figure 7-11. Zig-Zag Routing Example
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Requirement Units
41.9
0.15 (1) mm (ps)
0.15 (1) mm (ps)
41.9
Place GND vias as symmetrically as possible to data pair vias. GND via distance
should be placed less than 1x the diff pair via pitch
4
N/A
AC Cap
0.22
Voiding the plane directly under the pad
~0.1mm larger than the pad size is
required.
135 deg (a)
4x Trace width
1.5x
3x
Remove unwanted GND fill that is either floating or act like antenna
Void all layers of golden finger area
under the pad ~0.15mm larger than the
pad size is recommended.
Notes
Gen 4.0: -9.5 dB @ 8GHz
Gen 3.0: -8.2 dB @4GHz
ps Max distance from Device ball or
Connector pin to first PCB via.
Do trace length (delay) matching before
hitting discontinuities.
ps
Use micro via or back drilled via - no via
stub allowed.
Not Allowed
uF 20%, 0402 X5R or better. Only required
for TX pair when routed to connector.
Place close to TX side.
(See Figure 7-14)
S1 must be taken care in order to
consider Xtalk to adjacent pair. (
(See Figure 7-15)
DG-10931-001_v0.1 | 33
USB and PCIe