Figure 2-1. System Block Diagram - Nvidia Jetson AGX Xavier Series Design Manual

Figure 2-1. System Block Diagram
Jetson AGX Xavier
SYS_VIN_HV
SYS_VIN_MV
I2C 8x
AUD_MCLK
I2S x4
DSPK x2
DMIC x4
1
SPI 3x
UART 3x
CAN 2x
1
GPIOs
Debug: JTAG & UART
Safety (JAXi only):
VM I2C/IN T
TEMP_ALERT_OUT
(See note 1)
Notes:
1. SPI2, RGMII, GPIO31, and GPIO33 are available to use with a Safety MCU.
2. PCIe x8 interface and SLVS share the same pins.
Jetson AGX Xavier Series Product
Power Subsystem
PMIC
Regulators
Rail Discharge
Power/Vo ltage Monitors
Thermal
LPDDR4x eMMC
Sensor
Xavier SoC
USB 2.0 3x
USB 3.1 3x
UFS x1
UFS CLK/RST
PCIe: 2 x1, 1 x2,
2
1 x4, & 1 x8
HDMI_DP 3x
DP_AUX 3x
HPD 3x, CEC 1x
CSI: 4 x4, or 6 x2
CAM MCLK 2x
GP Clocks x2
2
SLVS 1 x8
(Not on JAXi)
SD CARD
1
RGMII
FAN
PWM 4x
Jetson AGX Xavier
DG-09840-001_v2.5 | 4