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REGISTER
NAME
CDR State Machine
Control
HEO_VEO_Lock
CDR State Machine
Control
SMPTE_Rate_Enable
SNLU183 – September 2015
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Table 7. CDR Registers (continued)
FIELD REGISTER
BITS
ADDRESS
Reg 0x3E Channel
7
INIT_CDR_SM_3
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Reg 0x69 Channel
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
hv_lckmon_cnt_ms[3]
2
hv_lckmon_cnt_ms[2]
1
hv_lckmon_cnt_ms[1]
0
hv_lckmon_cnt_ms[0]
Reg 0x6A Channel
7
INIT_CDR_SM_57
6
INIT_CDR_SM_56
5
INIT_CDR_SM_55
4
INIT_CDR_SM_54
3
INIT_CDR_SM_53
2
INIT_CDR_SM_52
1
INIT_CDR_SM_51
0
INIT_CDR_SM_50
Reg 0xA0 Channel
7
Reserved
6
Reserved
5
Reserved
4
dvb_enable
3
hd_enable
2
3G_enable
1
Reserved
0
Reserved
Copyright © 2015, Texas Instruments Incorporated
DEFAULT
R/RW
0x80
CDR State Machine Setting
At power-up, this bit needs to be set to
1
RW
0'b. See initialization set up
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0x0A
HEO/VEO Interval Monitoring
0
RW
0
RW
0
RW
0
RW
1
RW
While monitoring lock, this sets the
0
RW
interval time. Each interval is 6.5 ms. At
default condition, HEO_VEO Lock
1
RW
Monitor occurs once every 65 ms.
0
RW
0x44
CDR State Machine Control
0
RW
1
RW
0
RW
0
RW
At power-up, this register should be set
to 0x00. See initialization set up
0
RW
1
RW
0
RW
0
RW
0x1f
SMPTE_Data_Rate_Lock_Restriction
0
RW
0
RW
0
RW
1: Enable CDR Lock to 270 Mbps
1
RW
0: Disable CDR Lock to 270 Mbps
1: Enable CDR Lock to 1.485/1.4835
Gbps
1
RW
0: Disable CDR Lock to 1.485/1.4835
Gbps
1: Enable CDR Lock to 2.97/2.967 Gbps
1
RW
0: Disable CDR Lock to 2.97/2.967 Gbps
1
RW
Reserved
1
RW
Reserved
LMH0318 Programming Guide
Register Tables
DESCRIPTION
33
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