Texas Instruments LMH0318 Programmer's Manual page 28

Register Tables
REGISTER NAME
BST_Indx13
BST_Indx14
BST_Indx15
Active_EQ
EQ_Control
28
LMH0318 Programming Guide
Table 6. Receiver Registers (continued)
FIELD REGISTER
BITS
ADDRESS
Reg 0x4D Channel
7 I13_BST0[1]
6 I13_BST0[0]
5 I13_BST1[1]
4 I13_BST1[0]
3 I13_BST2[1]
2 I13_BST2[0]
1 I13_BST3[1]
0 I13_BST3[0]
Reg 0x4E Channel
7 I14_BST0[1]
6 I14_BST0[0]
5 I14_BST1[1]
4 I14_BST1[0]
3 I14_BST2[1]
2 I14_BST2[0]
1 I14_BST3[1]
0 I14_BST3[0]
Reg 0x4F Channel
7 I15_BST0[1]
6 I15_BST0[0]
5 I15_BST1[1]
4 I15_BST1[0]
3 I15_BST2[1]
2 I15_BST2[0]
1 I15_BST3[1]
0 I15_BST3[0]
Reg 0x52 Channel
7 eq_bst_to_ana[7]
6 eq_bst_to_ana[6]
5 eq_bst_to_ana[5]
4 eq_bst_to_ana[4]
3 eq_bst_to_ana[3]
2 eq_bst_to_ana[2]
1 eq_bst_to_ana[1]
0 eq_bst_to_ana[0]
Reg 0x55 Channel
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
INIT_CDR_SM_4
1
0 Reserved
Copyright © 2015, Texas Instruments Incorporated
DEFAULT R/RW
0xA5 Index13 4 Stage EQ Boost.
1 RW Index 13 Boost Stage 0 bit 1
0 RW Index 13 Boost Stage 0 bit 0
1 RW Index 13 Boost Stage 1 bit 1
0 RW Index 13 Boost Stage 1 bit 0
0 RW Index 13 Boost Stage 2 bit 1
1 RW Index 13 Boost Stage 2 bit 0
0 RW Index 13 Boost Stage 3 bit 1
1 RW Index 13 Boost Stage 3 bit 0
0xE6 Index14 4 Stage EQ Boost.
1 RW Index 14 Boost Stage 0 bit 1
1 RW Index 14 Boost Stage 0 bit 0
1 RW Index 14 Boost Stage 1 bit 1
0 RW Index 14 Boost Stage 1 bit 0
0 RW Index 14 Boost Stage 2 bit 1
1 RW Index 14 Boost Stage 2 bit 0
1 RW Index 14 Boost Stage 3 bit 1
0 RW Index 14 Boost Stage 3 bit 0
0xF9 Index15 4 Stage EQ Boost.
1 RW Index 15 Boost Stage 0 bit 1
1 RW Index 15 Boost Stage 0 bit 0
1 RW Index 15 Boost Stage 1 bit 1
1 RW Index 15 Boost Stage 1 bit 0
1 RW Index 15 Boost Stage 2 bit 1
0 RW Index 15 Boost Stage 2 bit 0
0 RW Index 15 Boost Stage 3 bit 1
1 RW Index 15 Boost Stage 3 bit 0
0x00 Active CTLE Boost Setting Read Back
0 R Read-back returns CTLE boost settings
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0x00 EQ Adaptation Control
0 R
0 RW
0 RW
0 RW
0 RW
0 RW
At power-up, this bit needs to be set to
0 RW
1'b. See initialization set up
0 RW
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DESCRIPTION
SNLU183 – September 2015
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