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For test purpose only, the register sequence below determines the correct CTLE setting. Note, the
selected CTLE setting produced by the test mode works for all of the data rates; therefore, this test should
be done at the highest data rate. The CTLE compensates for the media not the data rate. Additionally, for
3 Gbps or lower, register 0x55 specifies the fixed CTLE setting when operating in CTLE test mode.
RAW FF
04
RAW 2D
00
RAW 2C
40
RAW 3E
80
RAW 6A
44
RAW 31
20
RAW 0A
0C
RAW 0A
00
RAW 0C
00
RAW 02
18
RAR
52
xx
RAW 03
xx
RAW 2D
08
RAW 31
00
RAW 3E
00
RAW 6A
00
RAW 2C
00
SNLU183 – September 2015
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07
//Select Channel Registers
08
//Disable EQ over-ride
40
//Enable VEO scaling
80
//Enable HEO/VEO
FF
60
//Enable CTLE Test Mode to optimize eye opening
0C
//Reset CDR for the new settings to take place
0C
//Release CDR Reset
F0
//Setup register 0x0C to read lock indication
18
//Wait until bits [4:3] = 11'b to indicate CDR locked
FF
//Read EQ Boost setting and store in xx for normal mode of operation
FF
//Save EQ Boost setting in reg 0x03
08
//Enable the device to force EQ Setting from Reg 0x03
60
//Allow register 0x03 to control CTLE setting
80
//Restore initialization settings
FF
//Restore initialization settings
40
//Disable VEO scale
Copyright © 2015, Texas Instruments Incorporated
Device Configuration
LMH0318 Programming Guide
11
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