Table of Contents
Advertisement
Register Tables
REGISTER NAME
SD0_CONFIG
SD1_CONFIG
EQ_BOOST_OV
CTLE Setting
24
LMH0318 Programming Guide
Table 6. Receiver Registers (continued)
FIELD REGISTER
BITS
ADDRESS
Reg 0x14 Channel
7
Reserved
6
Reserved
5
sd_0_refa_sel[1]
4
sd_0_refa_sel[0]
3
sd_0_refd_sel[1]
sd_0_refd_sel[0]
2
1
Reserved
0
Reserved
Reg_0x15 Channel
7
Reserved
6
Reserved
5
sd_1_refa_sel[1]
4
sd_1_refa_sel[0]
3
sd_1_refd_sel[1]
sd_1_refd_sel[0]
2
1
Reserved
0
Reserved
Reg_0x2D Channel
7
Reserved
6
Reserved
5
Reserved
4
Reserved
reg_eq_bst_ov
3
2
Reserved
1
Reserved
0
Reserved
Reg_0x31 Channel
7
Reserved
6
adapt_mode[1]
adapt_mode[0]
5
4
Reserved
3
Reserved
2
Reserved
1
input_mux_ch_sel[1]
input_mux_ch_sel[0]
0
Copyright © 2015, Texas Instruments Incorporated
DEFAULT
R/RW
0x00
IN0 Signal Detect Threshold Setting
0
RW
0
RW
0
RW
Controls signal detect S
S
- De-Assert [3:2], thresholds for IN0
DL
0
RW
0000: Default levels (nominal)
0
RW
0101: Nominal -2 mV
1010: Nominal +5 mV
0
RW
1111: Nominal +3 mV
0
RW
0
RW
0x00
IN1 Signal Detect Threshold Setting
0
RW
0
RW
0
RW
Controls signal detect S
S
- De-Assert [3:2], thresholds for IN1
DL
0
RW
0000: Default levels (nominal)
0
RW
0101: Nominal -2 mV
1010: Nominal +5 mV
0
RW
1111: Nominal +3 mV
0
RW
0
RW
0x88
EQ Boost Override
1
RW
0
RW
0
RW
0
RW
1: Enable EQ boost over ride See
LMH0318 Programming Guide
1
RW
(SNLU183)
0: Disable EQ boost over ride
0
RW
0
RW
0
RW
CTLE Mode of Operation and
0x00
Input/Output Mux Selection
0
RW
00: Normal Operation - Manual CTLE
Setting
01: Test Mode - See the LMH0318
00
RW
Programming Guide (SNLU183) for
details
Other Settings - Invalid
0
RW
0
RW
0
RW
0
RW
IN0/1 and OUT0/1 selection
00: selects IN0 and OUT0/1
01: selects IN0 and OUT0
0
RW
10: selects IN1 and OUT1
11: selects IN1 and OUT0/1
www.ti.com
DESCRIPTION
- Assert [5:4],
DH
- Assert [5:4],
DH
SNLU183 – September 2015
Submit Documentation Feedback
Advertisement
Table of Contents
