Table of Contents
Advertisement
www.ti.com
REGISTER NAME
CDR_Status_1
Interrupt Status Register
SNLU183 – September 2015
Submit Documentation Feedback
Table 5. Global Registers (continued)
FIELD REGISTER
BITS
ADDRESS
Reg_0x02 Channel
7
Reserved
6
Reserved
5
Reserved
4
cdr_status[4]
3
cdr_status[3]
2
Reserved
1
Reserved
0
Reserved
Reg 0x54 Channel
Sigdet
7
cdr_lock_int
6
signal_det1_int
5
signal_det0_int
4
heo_veo_int
3
cdr_lock_loss_int
2
signal_det1_loss_int
1
signal_det0_loss_int
0
Copyright © 2015, Texas Instruments Incorporated
DEFAULT
R/RW
0x00
CDR Status
0
R
0
R
0
R
0
R
11: CDR locked
00: CDR not locked
0
R
0
R
0
R
0
R
0x00
Interrupt Status ( clears upon read )
1: Signal Detect from the selected
input asserted
0
R
0: Signal Detect from the selected
input de-asserted
1: CDR Lock interrupt
0
R
0: No interrupt from CDR Lock
1: IN1 Signal Detect interrupt
0
R
0: No interrupt from IN1 Signal Detect
1: IN0 Signal Detect interrupt
0
R
0: No interrupt from IN0 Signal Detect
1: HEO_VEO Threshold reached
0
R
interrupt
0: No interrupt from HEO_VEO
1: CDR loss of lock interrupt
0
R
0: No interrupt from CDR lock
1: IN1 Signal Detect loss interrupt
0
R
0: No interrupt from IN1 Signal Detect
1: IN0 Signal Detect loss interrupt
0
R
0: No interrupt from IN0 Signal Detect
LMH0318 Programming Guide
Register Tables
DESCRIPTION
21
Advertisement
Table of Contents
