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Register Tables
REGISTER
NAME
Full Temperature
Range
HEO_VEO_OV
EOM_CNTL
EOM_MSB
30
LMH0318 Programming Guide
Table 7. CDR Registers (continued)
FIELD REGISTER
BITS
ADDRESS
Reg 0x16 Channel
7
INIT_CDR_SM_27
6
INIT_CDR_SM_26
5
INIT_CDR_SM_25
4
INIT_CDR_SM_24
3
INIT_CDR_SM_23
2
INIT_CDR_SM_22
1
INIT_CDR_SM_21
0
INIT_CDR_SM_20
Reg 0x23 Channel
7
eom_get_heo_veo_ov
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Reg 0x24 Channel
7
fast_eom
6
Reserved
get_heo_veo_error_no_hi
5
ts
get_heo_veo_error_no_o
4
pening
3
Reserved
2
Reserved
1
eom_get_heo_veo
0
eom_start
Reg 0x25 Channel
7
eom_count[15]
6
eom_count[14]
5
eom_count[13]
4
eom_count[12]
3
eom_count[11]
2
eom_count[10]
1
eom_count[9]
0
eom_count[8]
Copyright © 2015, Texas Instruments Incorporated
DEFAULT
R/RW
0x7A
Temperature Range Setting
0
RW
1
RW
1
RW
1
RW
At power-up, this register needs to be
set to 0x25. See initialization set up
1
RW
0
RW
1
RW
0
RW
0x40
1: Enable reg 0x24[1] to acquire
HEO/VEO
0
RW
0: Disable reg 0x24[1] to acquire
HEO/VEO
1
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0x00
0x00
Eye Opening Monitor Control Register
1: Enable Fast EOM mode
0
R
0: Disable fast EOM mode
0
R
1: No zero crossing in the eye diagram
observed
0
R
0: Zero crossing in the eye diagram
detected
1: Eye diagram is completely closed
0
R
0: Open eye diagram detected
0
R
0
R
1: Acquire HEO & VEO(self-clearing)
0
RW
0: Normal operation
1: Starts EOM counter(self-clearing)
0
R
0: Normal operation
0x00
Eye opening monitor hits(MSB)
0
RW
0
RW
0
RW
0
RW
MSBs of EOM counter
0
RW
0
RW
0
RW
0
RW
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DESCRIPTION
SNLU183 – September 2015
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