Analog Signal Range - Teledyne ADQ8-4X Manual

All other interfaces operate on the data processing clock of the FPGA at 250 MHz. This clock is referred
to as the Data Clock.
See Section 5.1 for more details on the clock system.
1.2.6

Analog signal range

The analog signal range (
analog signal range it is depending on the gain setting. With for example a range of, 500 mV
log input signal can vary from –250 mV to +250 mV and the range can be moved from [–0 mV
+500 mV] to [–500 mV +0 mV] by the DC-offset feature,
The maximum digital code 2^15 represents an analog signal with a level
at the input. A specific analog signal
code:
DIGITAL_CODE_LEVEL = ANALOG_LEVEL / ( ACTUAL_ANALOG_RANGE / 2 ) * 2^15
A specific code
DIGITAL_CODE_LEVEL
ANALOG_LEVEL = ( DIGITAL_CODE_LEVEL / 2^15 ) * ( ACTUAL_ANALOG_RANGE / 2)
19-2302 A
2020-09-16
ACTUAL_ANALOG_RANGE
ANALOG_LEVEL
then represent the analog level as:
) is symmetrical around zero. The value of the
Section 2.3.
ACTUAL_ANALOG_RANGE / 2
will then be represented by the following digital
ADQ8-4X Manual
19-2302 A 2020-09-16
7(46)
, the ana-
pp
(1)
(2)
7(46)