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1
INTRODUCTION
The purpose of this manual is to explain how the digitizer is operated. The datasheet
eters for the specific versions of digitizer. References to software commands are made. In some places,
pseudo code is used for description. See
[3]
for general guidelines on programming the digitizer.
1.1 ADQ8-4X Architecture
The ADQ8-4X architecture is given in
information are also included.
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DESCRIPTION
a
Signal conditioning analog front-end.
b
High speed and high resolution A/D converters.
c
Calibration of gain and offset.
d
Teledyne SP Devices' proprietary technology for signal quality enhancement; DBS for
baseline stability in pulse data systems.
e
Acquisition engine that handles triggers and controls the data flow.
f
Data FIFO to buffer data before transmission to the host PC.
g
The data transfer to the host PC is through a PCIe Gen 2 interface.
h
Flexible clock generator.
i
Backplane clock reference for large scale integration.
i
Backplane clock triggers large scale integration.
Figure 1: ADQ8-4X architecture.
1.2 Fundamental design properties
There are some fundamental design properties that are necessary to understand before continuing.
1.2.1
Data format
The ADC components of ADQ8-4X has 10 bits resolution, while the data format inside the ADQ8-4X
and out to the host PC is 16 bits. The 16 bits from the ADCs are MSB aligned in this 16 bit data word.
Thus the 6 LSBs are zero.
19-2302 A
2020-09-16
[2]
for details on how to use the software commands and see
Figure
1. References to the corresponding sections with further
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19-2302 A 2020-09-16
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REFERENCE
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