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5
CLOCK
5.1 Clock domains
Different parts of the digitizer system operate on different clocks. The core of the clocking system is the
clock reference. This is the phase and frequency reference of the digitizer system. It is possible to use
different clock reference sources to meet the requirements of different applications.
The sampling clock is generated based on clock reference and drive the ADCs. This clock is important
for the signal quality since any timing deviation (jitter) will impact the actual time of the sample.
The trigger signal is sampled by a separate clock at a higher frequency than the sampling clock. This is
to achieve a good timing resolution of the trigger. This frequency is the highest in the digitizer and is
also the base for the timestamp.
The FPGA cannot operate at the high rate of the sampling clock. Instead the data processing operate
on a derived lower frequency denoted Data Clock and several samples are processed in parallel to
maintain the throughput. The Data Clock is also synchronized to the clock reference.
Finally the host PC interface also operate on a different clock. The PCIe system clock is provided from
the PCIe bus. This part of the design is not phase-locked to the sampling clock.
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DESCRIPTION
a
Clock reference.
b
Clock generator that generates several frequencies.
c
Various interfaces.
d
The ADC operates on sampling clock.
e
The trigger operates on the trigger clock.
f
Other interfaces operate on the Data Clock.
g
The FPGA operate on the Data Clock.
h
The host PC operate on an independent clock.
i
The clock generation for the host interface is from the
backplane.
Figure 21: Clock system overview
5.2 Flexible clock network
The preferred clock method is a systems design parameter and teh digitizer supports many options.
The clock system of the digitizer consist of two key parts; the clock reference and the clock generator.
The clock reference is a low frequency (10 MHz) high-precision and high-stability signal that sets the
accuracy of the clocks in the digitizer. The clock generator translates the frequency of the clock refer-
19-2302 A
2020-09-16
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TYPICAL FREQUENCIES
10 MHz
2 GHz
4 GHz
250 MHz
250 MHz
125 MHz (PCIe)
ADQ8-4X Manual
19-2302 A 2020-09-16
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REF
5.2
5.7
4.8
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