Bit And 32-Bit Data Exchanges (Xch, Xchp, Dxch, Dxchp) - Mitsubishi MELSEC QCPU Programming Manual

6 BASIC INSTRUCTIONS

6.4.7 16-bit and 32-bit data exchanges (XCH, XCHP, DXCH, DXCHP)

Internal Devices
Set
(System, User)
Data
Bit Word
D1
D2
[Instruction Symbol] [Execution Condition]
XCH, DXCH
XCHP, DXCHP
[Set Data]
Set Data
D1
D2
[Functions]
XCH
(1) Conducts 16-bit data exchange between
Before execution
After execution
DXCH
(1) Conducts 32-bit data exchange between
Before execution
After execution
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MELSECNET/10(H)
File Direct J \
Register
Bit
Command
Command
Head number of device storing data to be exchanged
D1
b15 b8 b7
0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1
D1
b15 b8 b7
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
+1
D1
b31 b16 b15
1 1 1 1 0 0 0 1 1 1
+1
D1
b31 b16 b15
0 0 0 0
1 1 1 1 1 1
QCPU
PLC CPU
Basic
High Performance
Usable Devices
Special
Function
Module
Word
U \G
indicates XCH/DXCH
Meaning
and .
D1 D2
b0 b15 b8
1 1 1 1 0 0 0 0
b0 b15 b8
0 1 1 1 0 0 0 0
+1, and +1,
D1 D1 D2
+1
D1 D2
b0 b31 b16
0 0 0 0 0 0 0 0 1 1 1
+1
D1 D2
b31 b16
b0
0 0 0
1 1 1 1 1 1 1 1
MELSEC-Q/QnA
QnA
Process CPU
Index
Constant
Register
K, H
Zn
D1 D2
P
D1 D2
Data Type
BIN 16/32 bits
D2
b7 b0
1 1 1 1 0 0 0 0
D2
b7 b0
0 0 0 0 0 1 1 1
.
D2
D2
b15 b0
1 1 1 1 1 1 1
D2
b15 b0
0 0 0 0
1 1 1
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