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6 BASIC INSTRUCTIONS
IMASK
(1) Enables/disables the execution of the interrupt program marked by the designated interrupt
pointer by using the bit pattern of 16 points from the device designated by
• 1 (ON) ......Interrupt program execution enabled
• 0 (OFF).....Interrupt program execution disabled
(2) The interrupt pointer numbers corresponding to the individual bits are as shown below:
(3) When the power is turned ON or when the CPU module has been reset, the execution of
interrupt programs I0 to I31,I48 to I255 is enabled, and the execution of interrupt programs I32
to I47 is disabled.
(4) The statuses of devices
and SD781 to SD793 (storage area for IMASK instruction mask pattern).
(5) Although the special registers are separated as SD715 to SD717 and SD781 to SD793, device
numbers should be designated as
POINTS
(1) An interrupt pointer occupies 1 step.
(2) Refer to the User's Manual (Function Explanation, Program Fundamentals) of the CPU
module in use for interrupt conditions.
(3) The DI state (interrupt disabled) is active during the execution of an interrupt program.
Do not insert EI instructions in interrupt programs to attempt the execution of multiple
interrupts, with interrupt programs running inside interrupt programs.
(4) If there are EI and DI instructions within a master control, these instructions will be
executed regardless of the execution/non-execution status of the MC instruction.
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b15
b14 b13 b12 b11 b10 b9
S
I15 I14
I13 I12 I11 I10
S
+ 1
I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16
+ 2
S
I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 I33 I32
+ 3
S
I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48
+ 4
S
I79 I78 I77 I76 I75 I74 I73 I72 I71 I70 I69
+ 5
S
I95 I94 I93 I92 I91 I90 I89 I88 I87 I86 I85 I84 I83 I82 I81 I80
+ 6
S
I111 I110 I109 I108 I107 I106 I105 I104 I103 I102 I101 I100 I99 I98 I97 I96
+ 7
S
I127 I126 I125 I124 I123 I122 I121 I120 I119 I118 I117 I116 I115 I114 I113 I112
+ 8
S
I143 I142 I141 I140 I139 I138 I137 I136 I135 I134 I133 I132 I131 I130 I129 I128
+ 9
S
I159 I158 I157 I156 I155 I154 I153 I152 I151 I150 I149 I148 I147 I146 I145 I144
+10
S
I175 I174 I173 I172 I171 I170 I169 I168 I167 I166 I165 I164 I163 I162 I161 I160
S
+11
I191 I190 I189 I188 I187 I186 I185 I184 I183 I182 I181 I180 I179 I178 I177 I176
S
+12
I207 I206 I205 I204 I203 I202 I201 I200 I199 I198 I197 I196 I195 I194 I193 I192
+13
S
I223 I222 I221 I220 I219 I218 I217 I216 I215 I214 I213 I212 I211 I210 I209 I208
+14
S
I239 I238 I237 I236 I235 I234 I233 I232 I231 I230 I229 I228 I227 I226 I225 I224
+15
S
I255 I254 I253 I252 I251 I250 I249 I248 I247 I246 I245 I244 I243 I242 I241 I240
,
+1,
S
S
S
I10
50
Stored at step 50
53
55
b8
b7
b6
b5
b4
b3
b2
I9
I8
I7
I6
I5
I4
I3
I2
I68 I67 I66 I65 I64
+2, and
+3 to
+15 are stored in SD715 to SD717
S
S
to
+15 successively.
S
S
X1C
X5
MELSEC-Q/QnA
.
S
b1
b0
I1
I0
Y10
Y30
IRET
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