Table of Contents
Advertisement
6 BASIC INSTRUCTIONS
IMASK
(1) Enables or disables the execution of the interrupt program marked by the designated interrupt
pointer by use of the bit pattern in the three points from the device designated by
• 1 (ON) ......... Interrupt program execution enabled
• 0 (OFF)........ Interrupt program execution disabled
(2) The interrupt pointer numbers corresponding to the individual bits are as shown below:
(3) When the power is turned ON, or when the CPU module has been reset, interrupt programs
from I0 to I31 are in the execution enabled state, and interrupt programs from I32 to I47 are in
the execution disabled state.
(4) The statuses of the
instruction mask pattern storage area).
POINTS
(1) An interrupt pointer occupies 1 step.
(2) Refer to the QnACPU Programming Manual (Fundamentals) for interrupt conditions.
(3) The DI state (interrupt disabled) is active during the execution of an interrupt program.
Do not insert EI instructions in interrupt programs to attempt the execution of multiple
interrupts, with interrupt programs running inside interrupt programs.
(4) If there are EI and DI instructions within a master control, these instructions will be
executed regardless of the execution/non-execution status of the MC instruction.
6 - 107
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
b15
b14 b13 b12 b11 b10 b9
S
I15 I14
I13 I12 I11 I10
+ 1
S
I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16
+ 2
S
I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 I33 I32
,
+1, and
S
S
S
T10
50
Stored at step 50
53
55
b8
b7
b6
b5
b4
b3
b2
I9
I8
I7
I6
I5
I4
I3
I2
+2 devices are stored from SD715 to SD717 (the IMASK
X1C
X5
MELSEC-Q/QnA
.
S
b1
b0
I1
I0
Y10
Y30
IRET
6 - 107
Advertisement
Table of Contents
