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Trigger/Store Condition with the trace label "DATA" The data
bus between the Emulator and the logic analyzer is 32 bit in width. The
condition which determines the enable bits depends on the data bus
width of the accessed area and the access size of the instruction. See the
below.
8/16/32-bit data bus area
Built-in ROM
Peripheral registers
and built-in RAM
Mnemonics in the Trace List Normally, trace list shows the
mnemonics for the instructions which were actually executed and does
not show mnemonics for such instructions that were fetched but not
executed.
However, mnemonics may not be displayed when the corresponding
instruction was actually executed, or vice versa.
This can be observed around the bottom of the trace list and when the store
condition is set.
Using the Logic Analyzer
Same as the processor
32-bit data bus area
32-bit data bus area (Long word access)
16-bit data bus area (Byte access and word
access)
Restrictions
55
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