Mitsubishi Electric MELCEC Q Series User Manual page 74

4. CPU MODULE
(continued)
I/O signal
Buffer memory
from the
address of the
master
master module
module
*1
–
Y(n+1A)
*1
–
Y(n+1B)
100 to 103
–
195
107
–
196 to 209
4
–
Item Setting range
Link priority, CPU priority
FROM/TO
Priority selection of
response
access to the master
specification
module buffer memory
Data clear
specification
Retention, clear (received
for
data)
communication
faulty station
M, L, B, T, C, D, W, R,
Faulty station
none (Bit device: multiples
detection
of 16)
Error No. T, C, D, W, R
• Test message sending
Line error • OFF data sending
check setting • Immediate data
(Line error) transmission before line
errors
*1 "n" is determined by the installation location of the master modules.
*2 When the total number of remote I/O station is odd, add 1 to the station number to obtain the
occupied storage devices.
(1) Link priority ..... Link access by MINI-S3 has the priority.
During the link access, FROM/TO is caused to wait.
• Possible to read out the received data refreshed at the
same timing.
• The maximum wait time (0.3ms + 0.2ms
separate refresh stations) for the FROM/TO instruction
may be generated.
(2) CPU priority ......
Even during the link access, it interrupts and
accesses.
• Depending on the timing, received data in the midst of
I/O refresh may be read.
• No wait time for FROM/TO instruction.
• Retention ......
• Clear ...... Sets all points to OFF.
• Sets the head device to store the faulty stations
detected data.
• MINI ...... occupies 4 words; MINI-S3: occupies 5 words.
• Sets the head device to store the error code at the error
occurrence.
• MINI ...... occupies 1 word; MINI-S3 ...... occupies (1+
number of remote terminal modules) words.
• Sets data sending method for verification of faulty area
when the line errors occur.
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Description
Access by FROM/TO instruction of
CPU has the priority.
Retains the received data for batch
and separate refresh.
number of