Panasonic FP7 User Manual page 105

 Programming method (Main program)
The interrupt for the CPU and the interrupt activation of the high-speed counter unit are
allowed in the main program. If the interrupt becomes disabled, clear the interrupt activation
request signal that is not processed in the unit as necessary.
R1
DF
（
R0
DF
（
R101
DF
（
R100
DF
（
R0
DF
（
R100
 Programming method (Interrupt program)
• Describe the program to be executed at the time of interrupt process in the interrupt program.
 Corresponding interrupt program number
Interrupt
Comparison match flag of
program
high-speed counter unit
No.
INTPG 10 CH0 Comparison match 0 flag
INTPG 11 CH0 Comparison match 1 flag
INTPG 12 CH1 Comparison match 0 flag
INTPG 13 CH1 Comparison match 1 flag
INTPG 14 CH2 Comparison match 0 flag
INTPG 15 CH2 Comparison match 1 flag
INTPG 16 CH3 Comparison match 0 flag
INTPG 17 CH3 Comparison match 1 flag
(Note 1): Interrupt program numbers are specified with slot numbers + (0 to 7).The numbers in the above table are for
the slot 1.
Example) The interrupt program number corresponding to the CH1 comparison match 1 flag of the slot number
1 is INTPG103.
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(Arbitrary program)
IMASK.US HFF
Enable INTPG 0-7.
IMASK.US H0
Disable INTPG 0-7.
ICLR.US HFF00
Clear INTPG 0-7.
INTPG10
IRET
Designation of the first operand of
IMASK and ICLR instructions
IMASK instruction
bit no. 15
Higher 8 bits 0: Fixed
ICLR instruction
bit no. 15
Higher 8 bits 1: Fixed
CPU
EI
Interrupt is enabled.
Interrupt is disabled.
DI
HSC unit
U1
Interrupt is enabled.
Slot No.
Interrupt is disabled.
U1
Slot No.
HSC unit
U1
Interrupt request is
Slot No.
cleared.
Interrupt program
10
Return
8 7
0 0 0 0 0 0 0 0
・
INTPG 7
・
0: Disable 1: Enable
INTPG 0
8 7
1 1 1 1 1 1 1 1
・
INTPG 7
0: Clear
・
1: Not clear
INTPG 0
0
0