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S3C6400X RISC MICROPROCESSOR
30
IIC-BUS INTERFACE
This chapter describes the functions and usage of IIC-BUS Interface in S3C6400X RISC microprocessor.
OVERVIEW
The S3C6400X RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data
line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are
connected to the IIC-bus. The SDA and SCL lines are bi-directional.
In multi-master IIC-bus mode, multiple S3C6400X RISC microprocessors can receive or transmit serial data to or
from slave devices. The master S3C6400X can initiate and terminate a data transfer over the IIC-bus. The IIC-bus
in the S3C6400X uses Standard bus arbitration procedure.
To control multi-master IIC-bus operations, values must be written to the following registers:
— Multi-master IIC-bus control register, IICCON
— Multi-master IIC-bus control/status register, IICSTAT
— Multi-master IIC-bus Tx/Rx data shift register, IICDS
— Multi-master IIC-bus address register, IICADD
When the IIC-bus is free, the SDA and SCL lines must be both at High level. A High-to-Low transition of SDA can
initiate a Start condition. A Low-to-High transition of SDA can initiate a Stop condition while SCL remains steady
at High Level.
The Start and Stop conditions can always be generated by the master devices. After the Start condition has been
initiated, the master selects the slave device by writing its 7-bit address in the first outgoing data byte. The 8th bit
determines the direction of the transfer (read or write).
Every data byte put onto the SDA line must be eight bits in total. There is no limit to send or receive bytes during
the bus transfer operation. Data is always sent first from most-significant bit (MSB) and every byte must be
immediately followed by acknowledge (ACK) bit.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
IIC-BUS INTERFACE
30-1
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